CY7C199CN-12VXAT Cypress Semiconductor Corp, CY7C199CN-12VXAT Datasheet
CY7C199CN-12VXAT
Specifications of CY7C199CN-12VXAT
Related parts for CY7C199CN-12VXAT
CY7C199CN-12VXAT Summary of contents
Page 1
... The device features an automatic power down feature that reduces power consumption when deselected. See the “Truth Table” on page 4 description of read and write modes. The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP package(s). Input Buffer RAM Array Power ...
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... Write Cycle 2 (CE controlled) Write Cycle 3 (WE controlled, OE low) Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 CY7C199CN .............................12 Page [+] Feedback ...
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... Pin Layout and Specifications 28 DIP Note 1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Document #: 001-06435 Rev TSOP 13.4 mm CY7C199CN 28 SOJ Page [+] Feedback ...
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... WE IOx X High-Z H Data Out L Data In H High-Z Selected, Outputs Disabled Description 0°C to 70°C –40°C to 85°C CY7C199CN SOJ TSOP 10, 11, 12, 13, 14, 15, 16, 17 18, 19, 20, 22, 23, 24, 25, 18 Mode Power Deselect/Power Down Stand Read Active (I ...
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... V , Output Disabled – ≤ V – Conditions T = 25° MHz 5 Conditions TSOP I Still air, soldered × 4.5 88.6 square inch, two–layer printed circuit board 21.94 CY7C199CN –15 –20 Unit Max Min Max V + 0 0.8 –0.5 0.8 V – 2.4 – ...
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... Resistor 3 R4 Resistor 4 R Resistor Thevenin TH V Voltage Thevenin TH Note 3. Tested initially and after any design or process change that may affect these parameters. Document #: 001-06435 Rev jig ita Description CY7C199CN & Nom Unit Ω 480 255 480 255 167 1.73 V Page ...
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... Condition = 2 ≥ – 0 ≥ V ≤ 0 – 0 less than less than t , and t HZCE LZCE HZOE LZOE “” on page 5. Transitions are measured ± 200 mV from steady state voltage. CY7C199CN –20 Unit Max 20 – ns – – ns – – – ns – – ns – ...
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... Timing Waveforms Data Retention Waveform CDR CE [9, 10] Read Cycle 1 Address Data Out Previous Data Valid Document #: 001-06435 Rev. *E DATA RETENTION MODE OHA CY7C199CN t R Data Valid Page [+] Feedback ...
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... Notes 9. Device is continuously selected CE HIGH for read cycle. 11. This cycle is OE controlled and WE is HIGH read cycle. 12. Address valid before or similar with CE transition LOW. Document #: 001-06435 Rev ACE t DOE t LZOE Data Valid t LZCE t PU 50% CY7C199CN t HZCE t HZOE High 50% Page [+] Feedback ...
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... Timing Waveforms (continued) [13, 14, 15] Write Cycle 1 (WE controlled) Address HZOE Undefined Data In/Out see footnotes Document #: 001-06435 Rev SCE PWE Data-In Valid CY7C199CN t HA Page [+] Feedback ...
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... During this period the IOs are in output state and input signals must not be applied. 16. This cycle is CE controlled. 17 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06435 Rev SCE Data-In Valid . CY7C199CN High Z Page [+] Feedback ...
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... OE low) Address Data Undefined In Out see footnotes Note 18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of t Document #: 001-06435 Rev. *E [18 SCE PWE t SD Data In Valid t HZWE and t . HZWE SD CY7C199CN Undefined See Footnotes t LZWE Page [+] Feedback ...
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... PX = 28-lead DIP (Pb-free 28-lead TSOP I (Pb-free) Speed low power CN = 0.25 µm Technology 99 = 256 K bit density with datawidth × 8 bits 1 = Fast Asynchronous SRAM family Technology Code CMOS 7 = SRAM CY = Cypress CY7C199CN Operating Power Option Range Standard Commercial Standard Commercial Low Power Industrial Standard ...
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... Package Diagrams Figure 1. 28-pin TSOP 13.4 mm), 51-85071 Document #: 001-06435 Rev. *E CY7C199CN 51-85071 *I Page [+] Feedback ...
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... Package Diagrams (continued) Figure 2. 28-pin (300 Mil) Molded SOJ, 51-85031 Document #: 001-06435 Rev. *E CY7C199CN 51-85031 *D Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 001-06435 Rev. *E Figure 3. 28-pin (300 Mil) PDIP, 51-85014 CY7C199CN 51-85014 *E Page [+] Feedback ...
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... Thin Small Outline Package VFBGA Very Fine-Pitch Ball Grid Array Document #: 001-06435 Rev. *E Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes mV milli Volts mW milli Watts MHz Mega Hertz pF pico Farad °C degree Celcius W Watts CY7C199CN Page [+] Feedback ...
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... Document History Page Document Title: CY7C199CN, 256 K (32 K × 8) Static RAM Document Number: 001-06435 Submission Revision ECN. Date ** 430363 See ECN *A 684342 See ECN *B 839904 See ECN *C 2896044 03/19/2010 *D 3108898 12/13/2010 *E 3198636 03/17/11 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...