CY8C3246PVI-141 Cypress Semiconductor Corp, CY8C3246PVI-141 Datasheet - Page 25

• Manufacturer Part Number: CY8C3246PVI-141
• Description: CY8C3246PVI-141
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3246PVI-141

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5-2. 8051 Internal Data Space
5.7.3 SFRs
The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory
space is shown in
Table 5-4. SFR Map
The CY8C32 family provides the standard set of registers found
on industry standard 8051 devices. In addition, the CY8C32
devices add SFRs to provide direct access to the I/O ports on the
device. The following sections describe the SFRs added to the
CY8C32 family.
XData Space Access SFRs
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
Document Number: 001-56955 Rev. *J
Address
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
0×D8
0×D0
0×C8
0×C0
0×F8
0×F0
0×E8
0×E0
0×B8
0×B0
0×A8
0×A0
0×98
0×90
0×88
0×80
0x1F
0x2F
0x7F
0xFF
0x00
0x20
0x30
0x80
SFRPRT15DR
B
SFRPRT12DR
ACC
SFRPRT6DR
PSW
SFRPRT5DR
SFRPRT4DR
–
SFRPRT3DR
IE
P2AX
SFRPRT2DR
SFRPRT1DR
–
SFRPRT0DR
Upper Core RAM Shared
(indirect addressing)
with Stack Space
Lower Core RAM Shared with Stack Space
Table
0/8
(direct and indirect addressing)
5-4.
4 Banks, R0-R7 Each
Bit-Addressable Area
SFRPRT15PS
–
SFRPRT12PS
–
SFRPRT6PS
–
SFRPRT5PS
SFRPRT4PS
–
SFRPRT3PS
–
–
SFRPRT2PS
SFRPRT1PS
SFRPRT0PS
SP
1/9
Special Function Registers
(direct addressing)
SFR
SFRPRT15SEL
SFRPRT12SEL
MXAX
–
SFRPRT6SEL
–
SFRPRT5SEL
SFRPRT4SEL
–
SFRPRT3SEL
–
SFRPRT1SEL
SFRPRT2SEL
–
SFRPRT0SEL
DPL0
2/A
In addition to the register or bit address modes used with the
lower 48 bytes, the lower 128 bytes can be accessed with direct
or indirect addressing. With direct addressing mode, the upper
128 bytes map to the SFRs. With indirect addressing mode, the
upper 128 bytes map to RAM. Stack operations use indirect
addressing; the 8051 stack space is 256 bytes. See the
“Addressing Modes”
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1.
During a MOVX instruction using the R0 or R1 register, the most
significant byte of the address is always equal to the contents of
MXAX, and the next most significant byte is always equal to the
contents of P2AX.
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX0
–
DPH0
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
3/B
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPL1
4/C
PSoC
section on page 11
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX1
–
DPH1
®
5/D
3: CY8C32 Family
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPS
6/E
Data Sheet
Page 25 of 119
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7/F
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