CY8CTST200A-48PVXI Cypress Semiconductor Corp, CY8CTST200A-48PVXI Datasheet - Page 204

• Manufacturer Part Number: CY8CTST200A-48PVXI
• Description: CY8CTST200A-48PVXI
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200A-48PVXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Processor Series: CY8CTxx2xxA
• Core: M8C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-3081-5

AMUX_CFG
21.3.17 AMUX_CFG
This register is used to configure the integration capacitor pin connections to the analog global bus.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 100
Bits
5
3:2
1:0
204
Individual Register Names and Addresses:
AMUX_CFG : 0,61h
Access : POR
Bit Name
0,61h
PRX_MODE
ICAPEN[1:0]
INTCAP[1:0]
Name
in the I/O Analog Mux chapter.
Analog Mux Configuration Register
7
6
Description
When this bit is set to 1, CS_CLK from TrueTouch counter logic block toggles regardless of the "EN"
bit setting in CS_CR0 register. When this bit is 0 CS_CLK is gated by "EN" bit in CS_CR0 register.
This bit is typically used in Proximity detection mode.
Bits connect internal capacitance to the analog global bus.
00b
01b
10b
11b
Select pins to enable connection of external integration capacitor in the charge integration mode.
00b
01b
10b
11b
PRX_MODE
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
No capacitance
Approximately 25 pF connected
Approximately 50 pF connected
Approximately 100 pF connected
Neither P0[3] or P0[1] enabled
P0[1] pin enabled
P0[3] pin enabled
Both P0[3] and P0[1] pins enabled
RW : 0
5
4
3
ICAPEN[1:0]
RW : 0
2
Register Definitions on
1
INTCAP[1:0]
RW : 0
0,61h
0
[+] Feedback