CY8CTST200A-48PVXI Cypress Semiconductor Corp, CY8CTST200A-48PVXI Datasheet - Page 45

• Manufacturer Part Number: CY8CTST200A-48PVXI
• Description: CY8CTST200A-48PVXI
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200A-48PVXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Processor Series: CY8CTxx2xxA
• Core: M8C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-3081-5

This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a
hardware resource in PSoC devices to change program execution to a new address without regard to the current task being
performed by the code being executed. For a quick reference of all PSoC registers in address order, refer to the
Reference chapter on page
5.1
A block diagram of the Interrupt Controller is shown in
interrupts.
This is the sequence of events that occur during interrupt
processing.
1. An interrupt becomes active, either because (a) the
2. The current executing instruction finishes.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
5. Interrupt Controller
interrupt condition occurs (for example, a timer expires),
(b) a previously posted interrupt is enabled through an
update of an interrupt mask register, or (c) an interrupt is
pending and GIE is set from ‘0’ to ‘1’ in the CPU Flag
register.
GPIO, etc.)
Interrupt
Source
(Timer,
Architectural Description
1
INT_CLRx:n Write
Interrupt Taken
187.
D
or
R
Q
Mask Bit Setting
Figure 5-1. Interrupt Controller Block Diagram
INT_MSKx
Interrupt
Posted
Pending
Interrupt
Figure
5-1, illustrating the concepts of posted interrupts and pending
3. The internal interrupt service routine (ISR) executes, tak-
■
■
■
■
ing 13 cycles. During this time, the following actions
occur:
The PCH, PCL, and Flag register (CPU_F) are pushed
onto the stack (in that order).
The CPU_F register clears. Since this clears the GIE bit
to ‘0’, additional interrupts are temporarily disabled.
The PCH (PC[15:8]) is cleared to zero.
The interrupt vector is read from the interrupt controller
and its value is placed into PCL (PC[7:0]). This sets the
program counter to point to the appropriate address in
the interrupt table (for example, 0014h for the GPIO
interrupt).
Encoder
Priority
CPU_F[0]
GIE
Interrupt Vector
Interrupt
Request
M8C Core
Register
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