CY8CTST200A-48PVXI Cypress Semiconductor Corp, CY8CTST200A-48PVXI Datasheet - Page 250

• Manufacturer Part Number: CY8CTST200A-48PVXI
• Description: CY8CTST200A-48PVXI
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200A-48PVXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Processor Series: CY8CTxx2xxA
• Core: M8C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-3081-5

INT_MSK0
21.3.59 INT_MSK0
This register enables the individual sources’ ability to create pending interrupts.
When an interrupt is masked off, the mask bit is ‘0’. The interrupt continues to post in the interrupt controller. Clearing the
mask bit only prevents a posted interrupt from becoming a pending interrupt. For additional information, refer to the
Definitions on page 48
Bit
7
6
5
4
3
2
1
0
250
Individual Register Names and Addresses:
INT_MSK0 : 0,E0h
Access : POR
Bit Name
0,E0h
I2C
Sleep
SPI
GPIO
Timer0
TrueTouch
Analog
V Monitor
Name
Interrupt Mask Register 0
RW : 0
I2C
7
in the Interrupt Controller chapter.
RW : 0
Sleep
6
Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Mask I2C interrupt.
Unmask I2C interrupt.
Mask Sleep interrupt.
Unmask Sleep interrupt.
Mask SPI interrupt.
Unmask SPI interrupt.
Mask GPIO interrupt.
Unmask GPIO interrupt.
Mask Timer0 interrupt.
Unmask Timer0 interrupt.
Mask TrueTouch interrupt.
Unmask TrueTouch interrupt.
Mask Analog interrupt.
Unmask Analog interrupt.
Mask Voltage Monitor interrupt.
Unmask Voltage Monitor interrupt.
RW : 0
SPI
5
0,E0h
RW : 0
GPIO
4
RW : 0
Timer0
3
TrueTouch
RW : 0
2
RW : 0
Analog
1
V Monitor
RW : 0
Register
0
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