CY8CTST200A-48PVXI Cypress Semiconductor Corp, CY8CTST200A-48PVXI Datasheet - Page 44

• Manufacturer Part Number: CY8CTST200A-48PVXI
• Description: CY8CTST200A-48PVXI
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200A-48PVXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Processor Series: CY8CTxx2xxA
• Core: M8C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-3081-5

4.2.6
The MVI Write Page Pointer Register (MVW_PP) sets the
effective SRAM page for MVI write memory accesses in a
multi-SRAM page PSoC device.
Bits 2 to 0: Page Bits[2:0]. These bits are only used by the
MVI [expr], A instruction, not to be confused with the
MVI A, [expr] instruction covered by the MVR_PP regis-
ter. This instruction is considered a write because data is
transferred from the microprocessor's A register (CPU_A) to
SRAM.
When an MVI
device with more than one page of SRAM, the SRAM
4.2.7
■
RAM Paging
44
0,D5h
Address
CPU_F Register on page
MVW_PP
MVW_PP Register
Related Registers
Name
[expr],
Bit 7
A instruction is executed in a
32.
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 4
address that is written by the instruction is determined by the
value of the least significant bits in this register. However,
the pointer for the MVI [expr], A instruction is always
located in the current SRAM page. See the PSoC Designer
Assembly Language User Guide for more information on the
MVI [expr], A instruction.
The function of this register and the MVI instructions are
independent of the SRAM Paging bits in the CPU_F register.
For additional information, refer to the
page
238.
Bit 3
Bit 2
Page Bits[2:0]
Bit 1
MVW_PP register on
Bit 0
Access
RW : 0
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