CYD18S72V18-167BGC Cypress Semiconductor Corp, CYD18S72V18-167BGC Datasheet - Page 27

CYD18S72V18-167BGC

CYD18S72V18-167BGC

Manufacturer Part Number
CYD18S72V18-167BGC
Description
CYD18S72V18-167BGC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYD18S72V18-167BGC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
18M (256K x 72)
Speed
167MHz
Interface
Parallel
Voltage - Supply
1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
484-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CYD18S72V18-167BGC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Table 14. SDR Mode (continued)
Notes
Document Number: 38-06082 Rev. *J
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
OHZ
CD1
CA1
CA2
DC
JIT
CQHQV
CQHQX
CKHZ1
CKLZ1
AC
CKHZA1
CKHZA2
CKLZA
SCINT
RCINT
SINT
RINT
BSY
49. Parameters specified with the load capacitance in
50. For the x18 devices, add 200 ps to this parameter in
51. Test conditions assume a signal transition time of 2 V/ns.
52. Add 300 ps to this timing for 36M devices.
53. Add 15% to this parameter if a VCORE of 1.5 V is used.
54. This parameter assumes input clock cycle to cycle jitter of ± 0ps.
Parameter
[54]
[49]
[49]
[49]
[49]
[54]
[54]
[49]
[49]
OE to high Z
C rise to DQ valid for flow through mode
(LowSPD = 0)
C rise to address readback valid for flow through
mode
C rise to address readback valid for pipelined mode
DQ output hold after C rise
Clock input cycle to cycle jitter
Echo clock (CQ) high to
output valid
Echo clock (CQ) high to
output hold
C rise to DQ output high Z in flow through mode
C rise to DQ output low Z in flow through mode
Address output hold after C rise
C rise to address output high Z for flow through
mode
C rise to address output high Z for pipelined mode 1.00
C rise to address output low Z
C rise to CNTINT low
C rise to CNTINT high
C rise to INT low
C rise to INT high
C rise to BUSY valid
Description
HSTL
1.8 V LVCMOS
2.5 V LVCMOS
3.3 V LVTTL
HSTL
1.8 V LVCMOS
2.5 V LVCMOS 3.3 V
LVTTL
Figure 9
Table
14.
and
Figure
10.
–0.70
–0.85
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
0.50
0.50
1.00
Min
–200
9.00
5.00
0.70
0.80
9.00
5.00
3.30
3.30
7.00
7.00
3.30
+/- 200
[50, 53]
[50, 53]
[50, 53]
9.00
Max
4.40
9.00
[53]
[53]
[50]
[50]
[53]
[53]
[53]
[53]
[53]
[53]
[53]
–0.80
–0.95
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
0.50
0.50
1.00
Min
–167
11.00
6.00
0.80
0.90
6.00
4.00
4.00
8.00
8.00
4.00
+/- 200
[50, 53]
[50, 53]
[50, 53]
11.00
11.00
11.00
Max
5.00
[53]
[53]
[50]
[50]
[53]
[53]
[53]
[53]
[53]
[53]
[53]
–0.90
–1.05
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
0.50
0.50
1.00
Min
–133
7.50
0.90
1.00
7.50
4.50
4.50
8.50
8.50
4.50
+/- 200
[50, 53]
[50, 53]
[50, 53]
13.00
13.00
13.00
13.00
Max
5.50
[53]
[53]
Page 27 of 52
FullFlex
[53]
[50]
[50]
[53]
[53]
[53]
[53]
[53]
[53]
Unit
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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