DAC1005D650HW/C1:5 NXP Semiconductors, DAC1005D650HW/C1:5 Datasheet - Page 22

• Manufacturer Part Number: DAC1005D650HW/C1:5
• Description: DAC1005D650HW/HTQFP100/TRAYBDP
• Manufacturer: NXP Semiconductors

Specifications of DAC1005D650HW/C1:5

• Settling Time: 20ns
• Number Of Bits: 10
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286776551

NXP Semiconductors
DAC1005D650
Product data sheet
10.4 Input clock
In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, see
“Interleaved mode timing (8x interpolation, latch on rising
The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and
Q channels.
SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse)
signal. The first data bits following the SELIQ rising edge are sent in channel I and the
following data bits are sent in channel Q. After this, the data is distributed alternately
between both channels.
The DAC1005D650 can operate with a clock frequency of 160 MHz in the Dual-port mode
and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see
can also be interfaced with CML (see
Fig 6.
Fig 7.
(asynchronous alternative 1)
(asynchronous alternative 2)
n in Qn = 9 and for In is 0 to 9.
Interleaved mode operation
Interleaved mode timing (8x interpolation, latch on rising edge)
(synchronous alternative)
Qn/SELIQ
All information provided in this document is subject to legal disclaimers.
In
Latch Q output
Latch I output
Rev. 2 — 3 September 2010
CLK
SELIQ
SELIQ
SELIQ
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
dig
In
LATCH
LATCH
Q
I
Figure 6 “Interleaved mode operation”
N
Figure
N + 1
2 ×
2 ×
XX
XX
FIR 1
FIR 1
9).
N + 2
2 ×
2 ×
FIR 2
FIR 2
N + 3
N + 1
edge)”.
N
DAC1005D650
N + 4
2 ×
2 ×
FIR 3
FIR 3
© NXP B.V. 2010. All rights reserved.
N + 5
N + 2
N + 3
001aaj586
Figure
and
001aaj814
Figure 7
8) but it
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