DSPIC33EP512MU810-I/PT Microchip Technology, DSPIC33EP512MU810-I/PT Datasheet - Page 133

• Manufacturer Part Number: DSPIC33EP512MU810-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 536KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
The
PIC24EPXXXGU810/814 interrupt controller reduces
the numerous peripheral interrupt request signals to a
single
dsPIC33EPXXXMU806/810/814
PIC24EPXXXGU810/814 CPU.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with a unique vector
• Fixed priority within a specified user priority level
• Fixed interrupt entry and return latencies
 2009-2011 Microchip Technology Inc.
traps
for each interrupt or exception source
Note 1: This data sheet summarizes the features
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
2: Some registers and associated bits
INTERRUPT CONTROLLER
interrupt
dsPIC33EPXXXMU806/810/814
of the dsPIC33EPXXXMU806/810/814
and PIC24EPXXXGU810/814 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer
(DS70600) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
to
request
Section
signal
6.
“Interrupts”
to
and
and
Preliminary
the
in
7.1
The
PIC24EPXXXGU810/814 Interrupt Vector Table (IVT),
shown in
starting at location 000004h. The IVT contains
seven non-maskable trap vectors and up to 114
sources of interrupt. In general, each interrupt source
has its own vector. Each interrupt vector contains a 24-
bit-wide address. The value programmed into each
interrupt vector location is the starting address of the
associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 takes priority over interrupts at any other
vector address.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The
PIC24EPXXXGU810/814 devices clear their registers
in response to a Reset, which forces the PC to zero.
The digital signal controller then begins program
execution at location 0x000000. A GOTO instruction at
the Reset address can redirect program execution to
the appropriate start-up routine.
Note:
Interrupt Vector Table
Reset Sequence
dsPIC33EPXXXMU806/810/814
dsPIC33EPXXXMU806/810/814
Figure
Any unimplemented or unused vector
locations
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
7-1, resides in program memory,
in
the
IVT
DS70616E-page 133
should
and
and
be