DSPIC33EP512MU810-I/PT Microchip Technology, DSPIC33EP512MU810-I/PT Datasheet - Page 139

• Manufacturer Part Number: DSPIC33EP512MU810-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 536KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 7-1:
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
Note 1:
R/W-0
R/W-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
OA
2:
3:
(3)
For complete register details, see
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15, user interrupts disabled)
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
IPL<2:0>
R/W-0
R/W-0
OB
SR: CPU STATUS REGISTER
(3)
(2)
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
SA
(3)
Register 3-1: “SR: CPU Status
R/W-0
R-0
SB
RA
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
C = Clearable bit
‘0’ = Bit is cleared
R/W-0
R/C-0
OAB
N
(2,3)
R/W-0
R/C-0
Register”.
SAB
OV
x = Bit is unknown
R/W-0
R -0
DA
Z
DS70616E-page 139
R/W-0
R/W-0
DC
C
bit 8
bit 0