DSPIC33EP512MU810-I/PT Microchip Technology, DSPIC33EP512MU810-I/PT Datasheet - Page 423

• Manufacturer Part Number: DSPIC33EP512MU810-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 536KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

27.0
FIGURE 27-1:
FIGURE 27-2:
 2009-2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
Shift Buffer
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
Data
2: Some registers and associated bits
PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
2: Polynomial length n is determined by ([PLEN<4:0>] + 1).
2 * F
of the dsPIC33EPXXXMU806/810/814
and PIC24EPXXXGU810/814 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “Program-
mable
(CRC)” (DS70346) of the “dsPIC33E/
PIC24E
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
P
Shift Clock
Cyclic
CRC BLOCK DIAGRAM
CRC SHIFT ENGINE DETAIL
Family Reference Manual”,
Redundancy
Bit 0
Read/Write Bus
CRCWDATH
CRCDATH
(4x32, 8x16 or 16x8)
CRC Shift Engine
X(1)
Variable FIFO
Shift Buffer
Check
(1)
CRCWDATH
0
Preliminary
in
1
Bit 1
CRCWDATL
CRCDATL
LENDIAN
The programmable CRC generator offers the following
features:
• User-programmable (up to 32nd order)
• Interrupt output
• Data FIFO
The programmable CRC generator provides a
hardware-implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable Interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in
engine is shown in
polynomial CRC equation
up to 32 bits
X(2)
Shift Complete Event
FIFO Empty Event
(1)
Figure
Bit 2
27-1. A simple version of the CRC shift
Figure
CRCWDATL
CRCISEL
27-2.
1
0
X(n)
Set CRCIF
(1)
DS70616E-page 423
Bit n
(2)