DSPIC33FJ12MC202-E/SP Microchip Technology, DSPIC33FJ12MC202-E/SP Datasheet - Page 187

12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt,MotorControl 2

DSPIC33FJ12MC202-E/SP

Manufacturer Part Number
DSPIC33FJ12MC202-E/SP
Description
12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt,MotorControl 2
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-E/SP

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REGISTER 19-1:
© 2009 Microchip Technology Inc.
bit 4
bit 3
bit 2-1
bit 0
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on
2: This feature is only available for the 16x BRG mode (BRGH = 0).
enabling the UART module for receive or transmit operation.
URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
UxMODE: UART
x
MODE REGISTER (CONTINUED)
Preliminary
dsPIC33FJ12MC201/202
DS70265D-page 185

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