DSPIC33FJ12MC202-E/SP Microchip Technology, DSPIC33FJ12MC202-E/SP Datasheet - Page 276

12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt,MotorControl 2

DSPIC33FJ12MC202-E/SP

Manufacturer Part Number
DSPIC33FJ12MC202-E/SP
Description
12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt,MotorControl 2
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-E/SP

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
dsPIC33FJ12MC201/202
TABLE 25-1:
DS70265D-page 274
Section 17.0 “Inter-Integrated
Circuit™ (I
Section 18.0 “Universal
Asynchronous Receiver
Transmitter (UART)”
Section Name
2
C™)”
MAJOR SECTION UPDATES
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 17.3 “I
• 17.4 “Baud Rate Generator” (retained Figure 17-1: I
• 17.5 “I
• 17.6 “Slave Address Masking”
• 17.7 “IPMI Support”
• 17.8 “General Call Address Support”
• 17.9 “Automatic Clock Stretch”
• 17.10 “Software Controlled Clock Stretching (STREN = 1)”
• 17.11 “Slope Control”
• 17.12 “Clock Arbitration”
• 17.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration
• 17.14 “Peripheral Pin Select Limitations
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 18.1 “UART Baud Rate Generator”
• 18.2 “Transmitting in 8-bit Data Mode
• 18.3 “Transmitting in 9-bit Data Mode
• 18.4 “Break and Sync Transmit Sequence”
• 18.5 “Receiving in 8-bit or 9-bit Data Mode”
• 18.6 “Flow Control Using UxCTS and UxRTS Pins”
• 18.7 “Infrared Support”
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 18-2).
2
2
C Interrupts”
C Module Addresses
Preliminary
Update Description
© 2009 Microchip Technology Inc.
2
C Block Diagram)

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