DSPIC33FJ32GP204-E/ML Microchip Technology, DSPIC33FJ32GP204-E/ML Datasheet - Page 104
DSPIC33FJ32GP204-E/ML
Manufacturer Part Number
DSPIC33FJ32GP204-E/ML
Description
16-bit DSC, 32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
5.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ32GP204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ12MC201-ISO PDF datasheet
- DSPIC33FJ16GP304-IPT PDF datasheet #2
- DSPIC33FJ16GP304-IPT PDF datasheet #3
- DSPIC33FJ16GP304-IPT PDF datasheet #4
- DSPIC33FJ32GP204-IPT PDF datasheet #5
- Current page: 104 of 284
- Download datasheet (4Mb)
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 8-2:
DS70290G-page 104
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
Note 1:
R/W-0
R/W-0
ROI
2:
PLLPOST<1:0>
This bit is cleared when the ROI bit is set and an interrupt occurs.
This register is reset only on a Power-on Reset (POR).
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: Processor Clock Reduction Select bits
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
DOZEN: DOZE Mode Enable bit
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide by 256
110 = FRC divide by 64
101 = FRC divide by 32
100 = FRC divide by 16
011 = FRC divide by 8
010 = FRC divide by 4
001 = FRC divide by 2
000 = FRC divide by 1 (default)
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output/8
10 = Reserved
01 = Output/4 (default)
00 = Output/2
Unimplemented: Read as ‘0’
R/W-0
R/W-1
CLKDIV: CLOCK DIVISOR REGISTER
CY
CY
CY
CY
CY
CY
CY
CY
/128
/64
/32
/16
/8 (default)
/4
/2
/1
y = Value set from Configuration bits on POR
W = Writable bit
‘1’ = Bit is set
DOZE<2:0>
R/W-1
U-0
—
R/W-1
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DOZEN
R/W-0
R/W-0
(2)
(1)
PLLPRE<4:0>
R/W-0
R/W-0
© 2011 Microchip Technology Inc.
FRCDIV<2:0>
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
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