DSPIC33FJ32GP204-E/ML Microchip Technology, DSPIC33FJ32GP204-E/ML Datasheet - Page 76
DSPIC33FJ32GP204-E/ML
Manufacturer Part Number
DSPIC33FJ32GP204-E/ML
Description
16-bit DSC, 32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
5.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ32GP204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ12MC201-ISO PDF datasheet
- DSPIC33FJ16GP304-IPT PDF datasheet #2
- DSPIC33FJ16GP304-IPT PDF datasheet #3
- DSPIC33FJ16GP304-IPT PDF datasheet #4
- DSPIC33FJ32GP204-IPT PDF datasheet #5
- Current page: 76 of 284
- Download datasheet (4Mb)
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 7-1:
REGISTER 7-2:
DS70290G-page 76
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 7-5
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
0’ = Bit is cleared
bit 3
Note 1:
R/W-0
IPL2
R/W-0
SATA
R-0
U-0
OA
—
2:
3:
2:
(2)
(3)
For complete register details, see
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS bit (INTCON1<15>) = 1.
For complete register details, see
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
R/W-0
IPL1
R/W-0
SATB
R-0
U-0
OB
—
SR: CPU STATUS REGISTER
CORCON: CORE CONTROL REGISTER
(2)
(3)
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R/W-0
SATDW
IPL0
R/W-1
R/C-0
U-0
SA
—
(2)
(3)
Register
Register
ACCSAT
R/W-0
R/W-0
R/C-0
R-0
SB
RA
US
3-1.
3-2.
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
-n = Value at POR
U = Unimplemented bit, read as ‘0’
(2)
IPL3
R/W-0
R/W-0
R/C-0
OAB
EDT
R-0
N
(2)
(2)
(1)
R/W-0
R/W-0
R/C-0
SAB
PSV
R-0
OV
© 2011 Microchip Technology Inc.
‘1’ = Bit is set
DL<2:0>
R/W-0
R/W-0
RND
R -0
R-0
DA
Z
R/W-0
R/W-0
R/W-0
R-0
DC
IF
C
bit 8
bit 0
bit 8
bit 0
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