EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 37
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EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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Overview
© November 2009 Altera Corporation
CYIV-51003-1.0
Cyclone
memory needs of Altera
structure consists of columns of M9K memory blocks that you can configure to
provide various memory functions, such as RAM, shift registers, ROM, and FIFO
buffers.
This chapter contains the following sections:
■
■
■
M9K blocks support the following features:
■
■
■
■
■
■
■
■
■
“Memory Modes” on page 3–7
“Clocking Modes” on page 3–14
“Design Considerations” on page 3–15
8,192 memory bits per block (9,216 bits per block including parity)
Independent read-enable (rden) and write-enable (wren) signals for each port
Packed mode in which the M9K memory block is split into two 4.5 K single-port
RAMs
Variable port configurations
Single-port and simple dual-port modes support for all port widths
True dual-port (one read and one write, two reads, or two writes) operation
Byte enables for data input masking during writes
Two clock-enable control signals for each port (port A and port B)
Initialization file to pre-load memory content in RAM and ROM modes
®
IV devices feature embedded memory structures to address the on-chip
3. Memory Blocks in Cyclone IV Devices
®
Cyclone IV device designs. The embedded memory
Cyclone IV Device Handbook, Volume 1
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