EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 375
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EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–5. Sample Reset Sequence for Bonded Configuration Receiver and Transmitter Channels—Receiver CDR in Manual
Lock Mode
Notes to
(1) For t
(2) The number of rx_locktorefclk[n] and rx_locktodata[n] signals depend on the number of channels configured. n=number of
(3) For t
(4) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
© December 2010 Altera Corporation
(rxurstpma) rx_analogreset
channels.
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
(rxurstpcs) rx_digitalreset
(txurstpcs) tx_digitalreset
Output Status Signals
CDR Control Signals
rx_locktorefclk[n] (2)
LTD_Manual
LTR_LTD_Manual
Figure
rx_locktodata[n] (2)
rx_locktorefclk[0]
rx_locktodata[0]
Reset Signals
2–5:
pll_locked
pll_areset
duration, refer to the
busy (4)
duration, refer to the
1
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. When the
receiver CDR is in manual lock mode, use the reset sequence shown in
As shown in
in manual lock mode configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal deasserted
during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the input reference clock.
1 µs
Cyclone IV Device Datasheet
2
Cyclone IV Device Datasheet
Figure
3
2–5, perform the following reset procedure for the receiver CDR
Two parallel clock cycles
4
5
chapter.
6
chapter.
t
LTR_LTD_Manual
(3)
7
7
7
7
t
LTD_Manual
(1)
Cyclone IV Device Handbook, Volume 2
8
Figure
2–5.
2–9
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