EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 419

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EP4CGX75DF27C7N

Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr

Specifications of EP4CGX75DF27C7N

Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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0
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–13. Option 1 for Receiver Core Clocking (Channel Reconfiguration Mode)
© December 2010 Altera Corporation
tx_clkout[0]
FPGA Fabric
Low-speed parallel clock (tx_clkout0)
High-speed serial clock generated by the MPLL
Figure 3–13
a transceiver block.
Option 2: Use the Respective Channel Transmitter Core Clocks
Enable this option if you want the individual transmitter channel’s tx_clkout
signal to provide the read clock to its respective Receive Phase Compensation
FIFO.
This option is typically enabled when all the transceiver channels have rate
matching enabled with different data rates and are reconfigured to another Basic
or Protocol functional mode with rate matching enabled.
shows the sharing of channel 0’s tx_clkout between all four channels of
Transceiver Block
TX0
RX0
TX1
RX1
TX2
RX2
TX3
RX3
Cyclone IV Device Handbook, Volume 2
MPLL
3–29

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