EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet - Page 39

• Manufacturer Part Number: EVAL-ADF7021-VDB2Z
• Description: 868 - 870MHz - EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of EVAL-ADF7021-VDB2Z

• Frequency: 868MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The calibration results are valid over changes in the ADF7021-V
supply voltage. However, there is some variation with temperature.
A typical plot of variation in image rejection over temperature
after initial calibrations at −40°C, +25°C, and +85°C is shown in
Figure 52. The internal temperature sensor on the ADF7021-V
can be used to determine whether a new IR calibration is required.
Figure 52. Image Rejection vs. Temperature After Initial Calibrations
60
50
40
30
20
10
0
–60
V
IFBW = 25kHz
WANTED SIGNAL:
RF FREQ = 430MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
DATA = PRBS9
f
LEVEL= –100dBm
DEV
DD
= 3.0V
= 4kHz
–40
CAL AT +85°C
at −40°C, +25°C, and +85°C
–20
RFIN
RFIN
TEMPERATURE (°C)
0
Figure 51. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller
INTERFERER SIGNAL:
RF FREQ = 429.8MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
DATA = PRBS11
f
DEV
CAL AT +25°C
20
= 4kHz
LNA
INTERNAL
SOURCE
40
SIGNAL
CAL AT –40°C
60
80
MUX
100
PHASE ADJUST
Rev. 0 | Page 39 of 60
PHASE ADJUST
REGISTER 5
GAIN ADJUST
REGISTER 5
FROM LO
I
ADF7021-V
I/Q GAIN/PHASE ADJUST AND
Q
RSSI MEASUREMENT
MICROCONTROLLER
ALGORITHM
PACKET STRUCTURE AND CODING
The suggested packet structure to use with the ADF7021-V is
shown in Figure 53.
See the Receiver Setup section for information about the required
preamble structure and length for the various modulation schemes.
PROGRAMMING AFTER INITIAL POWER-UP
Table 23 lists the minimum number of writes needed to set up
the ADF7021-V in either Tx or Rx mode after CE is brought
high for a minimum of 100 μs before programming any register.
Additional registers can also be written to tailor the part to a
particular application, such as setting up sync byte detection
or enabling AFC. When going from Tx to Rx or vice versa, the
user needs to toggle the Tx/Rx bit and write only to Register 0
to alter the LO by 100 kHz.
Table 23. Minimum Register Writes Required for Tx/Rx Setup
Mode
Tx
Rx
Tx to Rx and Rx to Tx
INTERFACE
SERIAL
PREAMBLE
4
4
POLYPHASE
IF FILTER
RSSI READBACK
Figure 53. Typical Format of a Transmit Protocol
WORD
SYNC
LOG AMP
7-BIT
ADC
RSSI/
Required Register Writes
Reg 1, Reg 3, Reg 0, Reg 2
Reg 1, Reg 3, Reg 5, Reg 0, Reg 4
Reg 0
FIELD
ID
DATA FIELD
ADF7021-V
CRC