EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet - Page 48

• Manufacturer Part Number: EVAL-ADF7021-VDB2Z
• Description: 868 - 870MHz - EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of EVAL-ADF7021-VDB2Z

• Frequency: 868MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7021-V
REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER
•
•
•
Baseband offset clock frequency (BBOS CLK) must be
greater than 1 MHz and less than 2 MHz, where
BBOS CLK = (XTAL/BBOS_CLK_DIVIDE)
Set the demodulator clock (DEMOD CLK) such that
2 MHz ≤ DEMOD CLK ≤ 15 MHz, where
DEMOD CLK = (XTAL/DEMOD_CLK_DIVIDE)
For 2FSK/3FSK, the clock/data recovery frequency (CDR
CLK) must be within 2% of (32 × data rate). For 4FSK, the
CDR CLK must be within 2% of (32 × symbol rate).
CDR CLK = (DEMOD CLK/CDR_CLK_DIVIDE)
GD6
0
0
...
1
AGC_CLK_DIVIDE
GD5
0
0
...
1
GD4
0
0
...
1
GD3
0
0
...
1
GD2
0
0
...
1
GD1
0
1
...
1
SEQ_CLK_DIVIDE
SK8
0
0
.
1
1
AGC_CLK_DIVIDE
INVALID
1
...
63
Figure 65. Register 3—Transmit/Receive Clock Register Map
SK7
0
0
.
1
1
...
...
...
...
...
...
SK3
0
0
.
1
1
SK2
0
1
.
1
1
Rev. 0 | Page 48 of 60
FS8
0
0
.
1
1
SK1
1
0
.
0
1
CDR_CLK_DIVIDE
FS7
0
0
.
1
1
SEQ_CLK_DIVIDE
1
2
.
254
255
...
...
...
...
...
...
•
•
The sequencer clock (SEQ CLK) supplies the clock to the
digital receive block. It should be as close to 100 kHz as
possible.
SEQ CLK = (XTAL/SEQ_CLK_DIVIDE)
The time allowed for each AGC step to settle is determined
by the AGC update rate. It should be set close to 3 kHz.
AGC Update Rate (Hz) = (SEQ CLK/AGC_CLK_DIVIDE)
FS3
0
0
.
1
1
FS2
0
1
.
1
1
FS1
1
0
.
0
1
OK4
0
0
...
1
DEMOD_CLK_
OK3
CDR_CLK_ DIVIDE
0
0
...
1
1
2
.
254
255
DIVIDE
OK2
0
0
...
1
OK1
0
1
...
1
BK2
0
0
1
1
DEMOD_CLK_DIVIDE
INVALID
1
...
15
BK1
0
1
0
1
BBOS_CLK_DIVIDE
4
8
16
32
ADDRESS
BITS