KSZ8842-PMBL AM TR Micrel Inc, KSZ8842-PMBL AM TR Datasheet - Page 18

• Manufacturer Part Number: KSZ8842-PMBL AM TR
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL AM TR

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Micrel, Inc.
October 2007
K2
H3
J3
K3
H4
J4
K4
H5
J5
K5
K6
J6
H6
K7
J7
H7
K8
J8
H8
K9
J9
K10
Ball
Number
IRDYN
TRDYN
STOPN
IDSEL
DEVSELN
REQN
GNTN
PERRN
SERRN
CBE3N
CBE2N
CBE1N
CBE0N
PAD31
PAD30
PAD29
PAD28
PAD27
PAD26
PAD25
PAD24
PAD23
Ball
Name
I/O
I/O
I/O
O
I
I/O
O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Type
PCI Initiator Ready
As a bus master, this signal is asserted low to indicate valid data phases on PAD [31:0]
during write data phases, indicates it is ready to accept data during read data phases. As a
target, it’ll monitor this IRDYN signal that indicates the master has put the data on the bus.
PCI Target Ready
As a bus target, this signal is asserted low to indicate valid data phases on PAD [31:0] during
read data phases, indicating it is ready to accept data during write data phases. As a master,
it will monitor this TRDYN signal that indicates the target is ready for data during read/write
operation.
PCI Stop
This signal is asserted low by the target device to stop the current transaction
PCI Initialization Device Select.
This signal is used to select the KSZ8842-PMQL/PMBL during configuration read and write
transactions.
PCI Device Select
This signal is asserted low when it is selected as a target during a bus transaction. As a bus
master, the KSZ8842-PMBL samples this signal to insure that the destination address for the
data transfer is recognized by a PCI target.
PCI Request
The KSZ8842-PMBL will assert this signal low to request PCI bus master operation.
PCI Grant
This signal is asserted low to indicate to the KSZ8842-PMBL that it has been granted the PCI
bus master operation.
PCI Parity Error
The KSZ8842-PMBL as a master or target will assert this signal low to indicate a parity error
on any incoming data. As a bus master, it will monitor this signal on all write operations.
PCI System Error
This system error signal is asserted low by the KSZ8842-PMBL.This signal is used to report
address parity errors.
Command and Byte Enable
These signals are multiplexed on the same PCI pins. During the address phase, these lines
define the bus command. During the data phase, these lines are used as Byte Enables. The
Byte enables are valid for the entire data phase and determine which byte lanes carry
meaningful data.
PCI Address / Data 31
Address and data are multiplexed on the all of the PAD balls. The PAD pins carry the
physical address during the first clock cycle of a transaction, and carry data during the
subsequent clock cycles.
PCI Address / Data 30
PCI Address / Data 29
PCI Address / Data 28
PCI Address / Data 27
PCI Address / Data 26
PCI Address / Data 25
PCI Address / Data 24
PCI Address / Data 23
Ball Function
18
KSZ8842-PMQL/PMBL
M9999-100207-1.5