KSZ8842-PMBL AM TR Micrel Inc, KSZ8842-PMBL AM TR Datasheet - Page 41

• Manufacturer Part Number: KSZ8842-PMBL AM TR
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL AM TR

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Micrel, Inc.
Configuration Revision Register (CFRV Offset 08H)
The CFRV register contains the KSZ8842-PMQL/PMBL revision number. The following table shows the CFRV register
bit fields.
Configuration Latency Timer Register (CFLT Offset 0CH)
This register configures the cache line size field and the latency timer.
The following table shows the CFLT register bit fields.
October 2007
31 – 16
31 – 24
23 – 16
15 – 8
15 – 8
7 – 0
7 – 4
3 – 0
Bit
Bit
Bit
2
1
0
Command
Command
Reserved
Type
Default
Default
0x00
0x00
0x00
0x02
0x00
0x00
0x1
0x0
Default
0
0
0
Description
Reserved
Configuration Latency Timer
Specifies, in units of PCI bus clocks, the value of the latency timer of the
KSZ8842-PMQL/PMBL. When the KSZ8842-PMQL/PMBL asserts FRAME_N,
it enables its latency timer to count. If the KSZ8842-PMQL/PMBL deasserts
FRAME_N prior to count expiration, the content of the latency timer is ignored.
Otherwise, after the count expires, the KSZ8842-PMQL/PMBL initiates
transaction termination as soon as its GNT_N is deasserted.
Cache Line Size
Specifies, in unit of 32-bit words (Dword), the system cache line size.
Description
Base Class
Indicates the network controller, and is equal to 2H.
Subclass
Indicates the Fast/Gigabit Ethernet chip, and is equal to 00H.
Reserved
Revision Number
Indicates the KSZ8842-PMQL/PMBL revision number, and is equal to 1H.
This number is incremented for subsequent revision.
Step Number
Indicates the KSZ8842-PMQL/PMBL step number, and is equal to 0H (chip
revision A). This number is incremented for subsequent KSZ8842-
PMQL/PMBL steps within the current revision.
Master Operation
When set, the KSZ8842-PMQL/PMBL is capable of acting as a bus
master.
When reset, the KSZ8842-PMQL/PMBL capability to generate PCI
accesses is disabled.
For normal operation, this bit must be set.
Memory Space Access
When set, the KSZ8842-PMQL/PMBL responds to memory space
accesses.
When reset, the KSZ8842-PMQL/PMBL does not respond to
memory space accesses.
Reserved
Description
41
KSZ8842-PMQL/PMBL
M9999-100207-1.5