KSZ8893MQL Micrel Inc, KSZ8893MQL Datasheet - Page 112
KSZ8893MQL
Manufacturer Part Number
KSZ8893MQL
Description
IC,Telecom Switching Circuit,CMOS,QFP,128PIN,PLASTIC
Manufacturer
Micrel Inc
Specifications of KSZ8893MQL
Controller Type
Ethernet Switch Controller
Interface
MII, RMII, SNI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1477-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8893MQL
Manufacturer:
Kendin
Quantity:
2 640
Company:
Part Number:
KSZ8893MQL
Manufacturer:
Micrel
Quantity:
947
Company:
Part Number:
KSZ8893MQL AM
Manufacturer:
Micrel
Quantity:
854
Company:
Part Number:
KSZ8893MQLI
Manufacturer:
SJK
Quantity:
12 000
Company:
Part Number:
KSZ8893MQLI
Manufacturer:
MICREL
Quantity:
15
Micrel, Inc.
KSZ8893MQL/MBL
Reset Circuit
The reset circuit in Figure 32 is recommended for powering up the KSZ8893MQL/MBL if reset is triggered only by
the power supply.
VCC
D1: 1N4148
D1
R 10K
KS8893M
RST
C 10uF
Figure 32. Recommended Reset Circuit
The reset circuit in Figure 33 is recommended for applications where reset is driven by another device (e.g., CPU,
FPGA, etc),.
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the
KSZ8893MQL/MBL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up.
VCC
R 10K
D1
KS8893M
CPU/FPGA
RST
RST_OUT_n
D2
C 10uF
D1, D2: 1N4148
Figure 33. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output
December 2007
112
M9999-121007-1.5