KSZ8893MQL Micrel Inc, KSZ8893MQL Datasheet - Page 39

• Manufacturer Part Number: KSZ8893MQL
• Description: IC,Telecom Switching Circuit,CMOS,QFP,128PIN,PLASTIC
• Manufacturer: Micrel Inc

Specifications of KSZ8893MQL

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1477-5

deferred state. If the port has packets to send during a backpressure situation, the carrier sense type
backpressure is interrupted and those packets are transmitted instead. If there are no additional packets to send,
carrier sense type backpressure is reactivated again until switch resources free up. If a collision occurs, the binary
exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of
further collisions and carrier sense is maintained to prevent packet reception.
To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following:
1. Aggressive back-off (register 3 (0x03), bit [0])
2. No excessive collision drop (register 4 (0x04), bit [3])
Note: These bits are not set as defaults, as this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8893MQL/MBL has an intelligent option to protect the switch system from receiving too many broadcast
packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of
switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8893MQL/MBL
has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are
programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67ms interval
for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the
rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in
register 6 (0x06) and 7 (0x07). The default setting is 0x63 (99 decimal). This is equal to a rate of 1%, calculated
as follows:
Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes
of preamble between two packets.
MII Interface Operation
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a
common interface between physical layer and MAC layer devices. The MII provided by the KSZ8893MQL/MBL is
connected to the device’s third MAC. The interface contains two distinct groups of signals: one for transmission
and the other for reception. The following table describes the signals used by the MII bus.
December 2007
PHY-Mode Connections
External MAC
Controller Signals
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63
KSZ8893MQL/MBL
PHY Signals
SMTXEN
SMTXER
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMTXC
SCOL
SCRS
SMRXDV
(not used)
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMRXC
Pin
Descriptions
Transmit enable
Transmit error
Transmit data bit 3
Transmit data bit 2
Transmit data bit 1
Transmit data bit 0
Transmit clock
Collision detection
Carrier sense
Receive data valid
Receive error
Receive data bit 3
Receive data bit 2
Receive data bit 1
Receive data bit 0
Receive clock
Table 3. MII Signals
39
MAC-Mode Connections
External
PHY Signals
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
KSZ8893MQL/MBL
MAC Signals
SMRXDV
(not used)
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMRXC
SCOL
SCRS
SMTXEN
SMTXER
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMTXC
M9999-121007-1.5