KSZ8893MQL Micrel Inc, KSZ8893MQL Datasheet - Page 28
![IC,Telecom Switching Circuit,CMOS,QFP,128PIN,PLASTIC](/photos/6/81/68152/576-128-pqfp_sml.jpg)
KSZ8893MQL
Manufacturer Part Number
KSZ8893MQL
Description
IC,Telecom Switching Circuit,CMOS,QFP,128PIN,PLASTIC
Manufacturer
Micrel Inc
Specifications of KSZ8893MQL
Controller Type
Ethernet Switch Controller
Interface
MII, RMII, SNI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1477-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8893MQL
Manufacturer:
Kendin
Quantity:
2 640
Company:
Part Number:
KSZ8893MQL
Manufacturer:
Micrel
Quantity:
947
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Part Number:
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Manufacturer:
Micrel
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Part Number:
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Manufacturer:
SJK
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12 000
Company:
Part Number:
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Manufacturer:
MICREL
Quantity:
15
Micrel, Inc.
KSZ8893MQL/MBL
Functional Description
The KSZ8893MQL/MBL contains two 10/100 physical layer transceivers and three MAC units with an integrated
Layer 2 managed switch.
The KSZ8893MQL/MBL has the flexibility to reside in either a managed or unmanaged design. In a managed
design, the host processor has complete control of the KSZ8893MQL/MBL via the SMI interface, MIIM interface,
2
SPI bus, or I
C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at
system reset time.
On the media side, the KSZ8893MQL/MBL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports,
and also 100BASE-FX on PHY port 1, which allows the KSZ8893MQL/MBL to be used as a media converter.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make
the design more efficient and allow for lower power consumption and smaller chip die size.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-
NRZI conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz
serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The
serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The
output current is set by an external1% 3.01KΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion,
data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel
conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the
twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer
must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial
estimation based on comparisons of incoming signal strength against some known cable characteristics, and then
tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as
temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is
then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed
by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to
the MAC.
PLL Clock Synthesizer
The KSZ8893MQL/MBL generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal
clocks are generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are
generated from an external 50MHz oscillator or system clock.
December 2007
28
M9999-121007-1.5