MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 22
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MCP3901A0-E/SS
Manufacturer Part Number
MCP3901A0-E/SS
Description
IC ENERGY METER AFE 2CH 20-SSOP
Manufacturer
Microchip Technology
Datasheets
1.MCP3901A0-ISS.pdf
(60 pages)
2.MCP3901A0-ISS.pdf
(30 pages)
3.MCP3901A0-ISS.pdf
(58 pages)
Specifications of MCP3901A0-E/SS
Number Of Bits
24
Number Of Channels
2
Power (watts)
10mW
Voltage - Supply, Analog
4.5 V ~ 5.5 V
Voltage - Supply, Digital
2.7 V ~ 5.5 V
Package / Case
20-SSOP (0.200", 5.30mm Width)
Ic Function
Analog Front End Device IC
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
SSOP
No. Of Pins
20
No. Of Channels
2
Input Voltage
2.2 V to 2.6 V
Mounting Style
SMD/SMT
Supply Voltage Max
5.5V
Rohs Compliant
Yes
Interface Type
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP3901A0-E/SS
Manufacturer:
Microchip
Quantity:
1 865
MCP3901
4.13
The MCP3901 incorporates two Delta-Sigma ADCs
with a multi-bit architecture. A Delta-Sigma ADC is an
oversampling converter that incorporates a built-in
modulator which is digitizing the quantity of charge
integrated by the modulator loop (see
quantizer is the block that is performing the
analog-to-digital conversion. The quantizer is typically
1-bit, or a simple comparator which helps to maintain
the linearity performance of the ADC (the DAC
structure is in this case inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The MCP3901’s 5-level quantizer is a flash ADC
composed of 4 comparators arranged with equally
spaced thresholds and a thermometer coding. The
MCP3901 also includes proprietary 5-level DAC
architecture that is inherently linear for improved THD
figures.
4.14
A Delta-Sigma converter is an integrating converter. It
also has a finite quantization step (LSB) which can be
detected by its quantizer. A DC input voltage that is
below the quantization step should only provide an all
zeros result since the input is not large enough to be
detected. As an integrating device, any Delta-Sigma
will show in this case idle tones. This means that the
output will have spurs in the frequency content that are
depending on the ratio between quantization step
voltage and the input voltage. These spurs are the
result of the integrated sub-quantization step inputs
that will eventually cross the quantization steps after a
long enough integration. This will induce an AC
frequency at the output of the ADC and can be shown
in the ADC output spectrum.
These idle tones are residues that are inherent to the
quantization process and the fact that the converter is
integrating at all times without being reset. They are
residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
are heavily signal dependent. They can degrade both
SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and thus difficult to filter from the actual input signal.
DS22192B-page 22
MCP3901 Delta-Sigma
Architecture
Idle Tones
Figure
5-1). The
For power metering applications, idle tones can be very
disturbing because energy can be detected even at the
50 or 60 Hz frequency, depending on the DC offset of
the ADCs, while no power is really present at the
inputs. The only practical way to suppress or attenuate
idle tones phenomenon is to apply dithering to the
ADC. The idle tones amplitudes are function of the
order of the modulator, the OSR and the number of
levels in the quantizer of the modulator. A higher order,
a higher OSR or a higher number of levels for the
quantizer will attenuate the idle tones amplitude.
4.15
In order to suppress or attenuate the idle tones present
in any Delta-Sigma ADCs, dithering can be applied to
the ADC. Dithering is the process of adding an error to
the ADC feedback loop in order to “decorrelate” the
outputs and “break” the idle tones behavior. Usually a
random or pseudo-random generator adds an analog
or digital error to the feedback loop of the delta-sigma
ADC in order to ensure that no tonal behavior can
happen at its outputs. This error is filter by the feedback
loop and typically has a zero average value so that the
converter static transfer function is not disturbed by the
dithering process. However, the dithering process
slightly increases the noise floor (it adds noise to the
part) while reducing its tonal behavior and thus
improving SFDR and THD. (See
Figure
tones into baseband white noise and ensures that
dynamic specs (SNR, SINAD, THD, SFDR) are less
signal dependent. The MCP3901 incorporates a
proprietary dithering algorithm on both ADCs in order to
remove idle tones and improve THD, which is crucial
for power metering applications.
2-14). The dithering process scrambles the idle
Dithering
© 2009 Microchip Technology Inc.
Figure 2-10
and