MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 48

• Manufacturer Part Number: MCP3901A0-E/SS
• Description: IC ENERGY METER AFE 2CH 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-E/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• No. Of Channels: 2
• Input Voltage: 2.2 V to 2.6 V
• Mounting Style: SMD/SMT
• Supply Voltage Max: 5.5V
• Rohs Compliant: Yes
• Interface Type: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3901
7.6
The configuration registers contain settings for the
internal clock prescaler, the oversampling ratio, the
channel 0 and channel 1 width settings of 16 or 24 bits,
REGISTER 7-6:
DS22192B-page 48
bit 15
Legend:
R = Readable bit
-n = Value at POR
bit 15:14
bit 13-12
bit 11:10
bit 9:8
bit 7:6
bit 5:4
bit 3:2
PRESCALE
RESET
R/W-0
R/W-0
_CH1
bit 7
<1>
Configuration Registers
PRESCALE<1:0> Internal Master Clock (AMCLK) Prescaler Value
11 = AMCLK = MCLK/ 8
10 = AMCLK = MCLK/ 4
01 = AMCLK = MCLK / 2
00 = AMCLK = MCLK (default)
OSR<1:0> Oversampling Ratio for Delta-Sigma A/D Conversion (all channels, DMCLK/DRCLK)
11 = 256
10 = 128
01 = 64 (default)
00 = 32
WIDTH<1:0> ADC Channel output data word width
1 = 24 bit mode
0 = 16 bit mode(default)
MODOUT<1:0>: Modulator Output Setting for MDAT pins
11 = Both CH0 and CH1 Modulator Outputs present on MDAT1 and MDAT0 pins
10 = CH1 ADC Modulator Output present on MDAT1 pin
01 = CH0 ADC Modulator Output present on MDAT0 pin
00 = No modulator output is enabled (default)
RESET<1:0>: RESET MODE SETTING FOR ADCs
11 = Both CH0 and CH1 ADC are in reset mode
10 = CH1 ADC in reset mode
01 = CH0 ADC in reset mode
00 = Neither Channel in reset mode(default)
SHUTDOWN<1:0>: SHUTDOWN MODE SETTING FOR ADCs
11 = Both CH0 and CH1 ADC in Shutdown
10 = CH1ADC in Shutdown
01 = CH0 ADC in Shutdown
00 = Neither Channel in Shutdown(default)
DITHER<1:0>: Control for dithering circuit
11 = Both CH0 and CH1 ADC have dithering circuit applied (default)
10 = Only CH1 ADC has dithering circuit applied
01 = Only CH0 ADC has dithering circuit applied
00 = Neither Channel has dithering circuit applied
PRESCALE
RESET
R/W-0
R/W-0
_CH0
<0>
CONFIGURATION REGISTERS:
CONFIG1: ADDRESS 0X0A, CONFIG2: ADDRESS 0X0B
W = Writable bit
‘1’ = Bit is set
SHUTDOWN
OSR<1>
R/W-0
R/W-0
_CH1
SHUTDOWN
OSR<0>
R/W-1
R/W-0
_CH0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
the modulator output control settings, the state of the
channel resets and shutdowns, the dithering algorithm
control (for idle tones suppression), and the control bits
for the external VREF and external CLK.
DITHER
WIDTH
R/W-0
R/W-1
_CH1
_CH1
DITHER
WIDTH
R/W-0
R/W-1
_CH0
_CH0
© 2009 Microchip Technology Inc.
x = Bit is unknown
VREFEXT
MODOUT
R/W-0
R/W-0
_CH1
MODOUT
CLKEXT
R/W-0
R/W-0
_CH0
bit 0
bit 8