MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 44
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MCP3901A0-E/SS
Manufacturer Part Number
MCP3901A0-E/SS
Description
IC ENERGY METER AFE 2CH 20-SSOP
Manufacturer
Microchip Technology
Datasheets
1.MCP3901A0-ISS.pdf
(60 pages)
2.MCP3901A0-ISS.pdf
(30 pages)
3.MCP3901A0-ISS.pdf
(58 pages)
Specifications of MCP3901A0-E/SS
Number Of Bits
24
Number Of Channels
2
Power (watts)
10mW
Voltage - Supply, Analog
4.5 V ~ 5.5 V
Voltage - Supply, Digital
2.7 V ~ 5.5 V
Package / Case
20-SSOP (0.200", 5.30mm Width)
Ic Function
Analog Front End Device IC
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
SSOP
No. Of Pins
20
No. Of Channels
2
Input Voltage
2.2 V to 2.6 V
Mounting Style
SMD/SMT
Supply Voltage Max
5.5V
Rohs Compliant
Yes
Interface Type
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP3901A0-E/SS
Manufacturer:
Microchip
Quantity:
1 865
MCP3901
7.3
The PHASE register (PHASE<7:0>) is a 7 bits + sign
MSB first two's complement register that indicates how
much phase delay there should be between Channel 0
and Channel 1.
The reference channel for the delay is channel 1
(typically the voltage channel when used in energy
metering applications), i.e. when PHASE register code
is positive, Channel 0 is lagging channel 1.
When PHASE register code is negative, Channel 0 is
leading versus Channel 1.
The delay is give by the following formula:
EQUATION 7-1:
REGISTER 7-3:
DS22192B-page 44
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7:0
PHASE<7>
R/W-0
PHASE Register
Delay
CH0 relative to CH1 phase delay
Delay = PHASE Register two’s complement code / DMCLK (Default PHASE=0)
PHASE<6>
=
R/W-0
Phase Register Code
------------------------------------------------- -
PHASE REGISTER (PHASE): ADDRESS 0X07
DMCLK
W = Writable bit
‘1’ = Bit is set
PHASE<5>
R/W-0
PHASE<4> PHASE<3>
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
7.3.1
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration (MCLK=4 MHz). The
PHASE register coding depends on the OSR setting:
• OSR=256: the delay can go from -128 to +127.
• OSR=128: the delay can go from -64 to +63.
• OSR=64: the delay can go from -32 to +31.
• OSR=32: the delay can go from -16 to +15.
PHASE<7> is the sign bit. Phase<6> is the MSB
and PHASE<0> the LSB
PHASE<6> is the sign bit. Phase<5> is the MSB
and PHASE<0> the LSB
PHASE<5> is the sign bit. Phase<4> is the MSB
and PHASE<0> the LSB
PHASE<4> is the sign bit. Phase<3> is the MSB
and PHASE<0> the LSB
PHASE<2>
PHASE RESOLUTION FROM OSR
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
PHASE<1>
R/W-0
PHASE<0>
R/W-0
bit 0