MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 24

• Manufacturer Part Number: MCP3901A0-E/SS
• Description: IC ENERGY METER AFE 2CH 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-E/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• No. Of Channels: 2
• Input Voltage: 2.2 V to 2.6 V
• Mounting Style: SMD/SMT
• Supply Voltage Max: 5.5V
• Rohs Compliant: Yes
• Interface Type: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3901
A data ready pulse will not be generated by any ADC
while in reset mode.
Reset mode also effects the modulator output block,
i.e. the MDAT pin, corresponding to the channel in
reset. If enabled, it provides a bitstream corresponding
to a zero output (a series of 0011 bits continuously
repeated).
When an ADC exists ADC reset mode, any phase
delay present before reset was entered will still be
present. If one ADC was not in reset, the ADC leaving
reset mode will resynchronize automatically the phase
delay relative to the other ADC channel per the phase
delay register block and give DR pulses accordingly.
If an ADC is placed in Reset mode while the other is
converting, it is not shutting down the internal clock.
When going back out of reset, it will be resynchronized
automatically with the clock that did not stop during
reset.
If both ADCs are in soft reset or shutdown modes, the
clock is no longer distributed to the digital core for low
power operation. Once any of the ADC is back to
normal operation, the clock is automatically distributed
again.
4.20
This mode is only available during a POR or when the
RESET pin is pulled low. The RESET pin low state
places the device in a hard reset mode.
In this mode all internal registers are reset to their
default state.
The DC biases for the analog blocks are still active, i.e.
the MCP3901 is ready to convert. However, this pin
clears all conversion data in the ADCs. In this mode the
MDAT outputs are in high impedance. The comparators
outputs of both ADCs are forced to their reset state
(0011). The SINC filters are all reset as well as their
double output buffers. See serial timing for minimum
pulse
Characteristics”.
During a hard reset, no communication with the part is
possible. The digital interface is maintained in a reset
state.
4.21
ADC shutdown mode is defined as a state where the
converters and their biases are off, consuming only
leakage current. After this is removed, start-up delay
time (SINC filter settling time will occur before
outputting meaningful codes. The start-up delay is
needed to power-up all DC biases in the channel that
was in shutdown. This delay is the same than t
any DR pulse coming within this delay should be
discarded.
DS22192B-page 24
low
Hard Reset Mode (RESET = 0)
ADC Shutdown Mode
time,
in
Section 1.0
“Electrical
POR
and
Each converter can be placed in shutdown mode
independently. The CONFIG registers are not modified
by the shutdown mode. This mode is only available
through programming of the SHUTDOWN<1:0> bits
the CONFIG2 register.
The output data is flushed to all zeros while in ADC
shutdown. No data ready pulses are generated by any
ADC while in ADC shutdown mode.
ADC shutdown mode also effects the modulator output
block, i.e. if MDAT of the channel in shutdown mode is
enabled, this pin will provide a bitstream corresponding
to a zero output (series of 0011 bits continuously
repeated).
When an ADC exits ADC shutdown mode, any phase
delay present before shutdown was entered will still be
present. If one ADC was not in shutdown, the ADC
leaving
automatically the phase delay relative to the other ADC
channel per the phase delay register block and give DR
pulses accordingly.
If an ADC is placed in Shutdown mode while the other
is converting, it is not shutting down the internal clock.
When going back out of shutdown, it will be
resynchronized automatically with the clock that did not
stop during reset.
If both ADCs are in ADC reset or ADC shutdown
modes, the clock is no more distributed to the digital
core for low power operation. Once any of the ADC is
back to normal operation, the clock is automatically
distributed again.
4.22
The lowest power consumption can be achieved when
SHUTDOWN<1:0>=11, VREFEXT=CLKEXT=1. This
mode is called “Full shutdown mode”, and no analog
circuitry is enabled. In this mode, the POR A
monitoring circuit is also disabled. When the clock is
idle (CLKI = 0 or 1 continuously), no clock is propa-
gated throughout the chip. Both ADCs are in shutdown,
the internal voltage reference is disabled and the inter-
nal oscillator is disabled.
The only circuit that remains active is the SPI interface
but this circuit does not induce any static power
consumption. If SCK is idle, the only current
consumption comes from the leakage currents induced
by the transistors and is less than 1 µA on each power
supply.
This mode can be used to power down the chip
completely and avoid power consumption when there
is no data to convert at the analog inputs. Any SCK or
MCLK edge coming while on this mode will induce
dynamic power consumption.
Once any of the SHUTDOWN, CLKEXT and VREFEXT
bits returns to 0, the POR AV
back to operation and AV
Full Shutdown Mode
shutdown
© 2009 Microchip Technology Inc.
mode
DD
monitoring can take place.
DD
will
monitoring block is
resynchronize
VDD