AD9788-EBZ Analog Devices Inc, AD9788-EBZ Datasheet - Page 4
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AD9788-EBZ
Manufacturer Part Number
AD9788-EBZ
Description
BOARD EVAL FOR AD9788
Manufacturer
Analog Devices Inc
Series
TxDAC®r
Datasheet
1.AD9785BSVZ.pdf
(64 pages)
Specifications of AD9788-EBZ
Design Resources
Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
Number Of Dac's
2
Number Of Bits
16
Outputs And Type
2, Differential
Sampling Rate (per Second)
800M
Data Interface
Serial
Settling Time
22ms
Dac Type
Current
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9788
Silicon Manufacturer
Analog Devices
Application Sub Type
DAC
Kit Application Type
Data Converter
Silicon Core Number
AD9788
Kit Contents
Board
Development Tool Type
Hardware - Eval/Demo Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9785/AD9787/AD9788
DIGITAL SPECIFICATIONS
T
otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
LVDS INPUT (SYNC_I+, SYNC_I−)
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
DAC CLOCK INPUT (REFCLK+, REFCLK–)
MAXIMUM INPUT DATA RATE
SERIAL PERIPHERAL INTERFACE
INPUT DATA
MIN
REFCLK Frequency Range, PLL Enabled
Input V
Input V
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
LVDS Input Rate (f
Setup Time, SYNC_I to DAC Clock
Hold Time, SYNC _I to DAC Clock
Output Voltage High, V
Output Voltage Low, V
Output Differential Voltage, |V
Output Offset Voltage, V
Output Impedance, Single-Ended, R
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
1× Interpolation
2× Interpolation
4× Interpolation
8× Interpolation
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time, SPI_SDIO to SCLK
Hold Time, SPI_SDIO to SCLK
Setup Time, SPI_CSB to SCLK
Data Valid, SPI_SDO to SCLK
Setup Time, Input Data to DATACLK
Hold Time, Input Data to DATACLK
Setup Time, Input Data to REFCLK
Hold Time, Input Data to REFCLK
to T
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
DVDD18 = 1.8 V ±5%
DVDD18 = 1.9 V ± 5%
MAX
IN
IN
Logic High
Logic Low
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
SYNC_I
OA
IA
= f
OA
OS
or V
or V
or V
DATA
IB
OB
)
OB
IDTH
IDTHH
OD
|
− V
O
IDTHL
IN
Test Conditions/Comments
SYNC_I+ = V
SYNC_O+ = V
All modes, −40°C to +85°C
Rev. A | Page 4 of 64
1A
OA
, SYNC_I− = V
, SYNC_O− = V
1
1B
OB
, 100 Ω termination
OUTFS
= 20 mA, maximum sample rate, unless
Min
825
–100
80
825
1025
150
1150
80
112.5
−0.25
2.0
30
0.45
0.25
400
300
800
900
30
200
225
100
40
12.5
12.5
2.8
0.0
3.0
10.0
460
−1.5
2.4
Typ
20
200
100
800
400
250
250
Max
0.8
1575
+100
120
1575
250
1250
120
1600
500
250
Unit
V
V
mV
mV
mV
Ω
MHz
ns
ns
mV
mV
mV
mV
Ω
mV
mV
MHz
MHz
MHz
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns