CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 16

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

On-Chip BandGap Reference and Current Biasing
For current biasing and voltage reference requirements for the
AFEs, ADCs, and LVDS I/O, LUPA 3000 includes a bandgap
voltage reference that is typically 1.25V. This reference is used
to generate the differential Vrefp–Vrefm ADC reference and a
analog voltage reference for the LVDS driver I/O.
The bandgap reference voltage also forms a stable current
reference for the LVDS drivers and bias currents for all of the
analog amplifiers. A “Current-Ref_2” pin is included on the
package to allow connection of an ~ 50K resistor (±1%) to gnd
to realize a desired 25A current sourced from the LUPA 3000
device. A buffered version of the internal bandgap reference is
monitored at this pin.
An optional mode is available to enable an external bandgap
regulator. Control bits in SPI register 74 (decimal) allow this
feature. Bit 2 is a power down control bit for the internal bandgap.
Setting this bit high along with bit 1 (int_res), and bit 0
(bg_disable), allow driving the “Current_Ref_2” pin with an
external reference. An internal current reference resistor of 50K
to ground is applied (This mode has reduced current accuracy
(~ ± 10% from the external resistor mode (± 1%).
Table 13. Reference and Bias Parameters
Document Number: 001-44335 Rev. *C
Vrefp
Vrefm
Vrefp–Vrefm
Vcm
Current_Ref_2
BandGap Reference (internal) 1.25 V ± 0.05 V at 2.5 V, T = 40 °C Typical < 50 PPM. Level and tracking are 3 bit SPI trimmable.
Parameter
1.7 V to 1.75 V
0.8 V to 0.75 V
0.95 V to 1.0 V (difference)
0.9 V
1.25 V ± 0.1 V at 25 µA to gnd
Parameter Value (Typical)
PRELIMINARY
At Vdd=2.5 V. Requires 0.01 µF to gnd.
At Vdd=2.5 V. Requires 0.01 µF to gnd.
ADC range. 3 bit SPI trim settings 1x, 0.95x, 0.91x, 0.83x, 0.77x,
0.71x, 0.67x, 0.5x.
External power supply voltage. Requires 10 nF to gnd. Refer to
Table 43
Must pull down to gnd with ~ 50 kΩ.
Five settings at ~ 1.2% adjust per step.
Five trimming levels for the internal bandgap voltage are
available through bits 2:0 of SPI register 64 (decimal). This
allows minor adjustment in process variations for voltage level
and temperature tracking. A POR value is preset so that user
adjustment is not required (see the register definition for exact
settings). Each setting adjusts an internal resistor value used to
adjust the PTAT (proportional to absolute temperature) “K” factor
ratio. Each of the five settings affect the “K” trimming factor by ~
1.2%. Minor adjustments are made to tune the reference voltage
level and temperature tracking rate to compensate for IC
processing variations.
The reference generation circuits also form the internal analog
common mode voltage for the differential analog circuits. The
Vcm level is available at a package pin for external decoupling
and should be driven by a 0.9V supply (refer to Table 43 on
page 31). The Vdark or “black” level reference supplied from an
on-chip SPI programmable DAC is also buffered and distributed
on-chip as input to each of the 64 AFE and ADC channels. This
signal is also available at a package pin for external decoupling.
Separate power down control bits are available for the differential
ADC reference (Vrefp–Vrefm), Vcm, and Vdark. When any of
these are powered down, external references are driven on the
external package pins.
for the references and biases.
on page 31.
Table 13
Comment
overviews primary parameters
CYIL1SN3000AA
Page 16 of 61
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