CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 17

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sequencer and Logic
The sequencer generates the internal timing of the image core based on the SPI settings uploaded by the user. The user controls the
following settings:
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Table 14. Detailed Description of SPI Registers
Document Number: 001-44335 Rev. *C
Window resolution
FOT and ROT
Enabling or disabling reduced ROT mode
Readout modes (training, test image, and normal)
Address
10
12
13
14
15
16
17
30
31
11
0
1
2
3
4
5
6
7
8
9
<5:0>
<5:4>
<4:0>
<7:0>
<7:0>
<7:0>
<7:0>
<5:0>
<7:0>
<2:0>
<7:0>
<2:0>
<4:0>
<1:0>
<7:0>
<6:0>
<7:0>
<3:0>
<7:4>
<7:0>
<3:0>
<7:4>
<7:0>
<3:0>
<7:4>
<7:0>
<7:0>
Bits
<0>
<1>
<2>
<3>
<0>
<1>
<2>
SEQUENCER
Power down
Reset_n_seq
Red_rot
Ds_en
Sel_pre_width
ROT_TIMER
PRECHARGE_TIMER
SAMPLE_TIMER
VMEM_TIMER
FOT_TIMER
NB_OF_KERNELS
Y_START <7:0>
Y_START <10:8>
Y_END <7:0>
Y_END <10:8>
X_START
TRAINING
Training_en
Bypass_en
Analog_out_en
BLACK_REF
BIAS_COL_LOAD
BIASING_CORE_1
Bias_col_amp
Bias_col_outputamp
BIASING_CORE_2
Bias_sel_pre
Bias_analog_out
BIASING_CORE_3
Bias_decoder_y
Bias_decoder_x
FIXED
CHIP_REV_NB
PRELIMINARY
Name
Power down analog core
Reset_n of on chip sequencer
Enable reduced ROT mode
Enable DS operation
Width of sel_pre pulse
Length of ROT
Length of pixel precharge in clk/4
Length of pixel sample in clk/4
Length of pixel vmem in clk/4
Length of FOT in clk/4
Number of kernels to readout
Start pointer Y readout
End pointer Y readout
Start pointer X
1: transmit training pattern; 0: transmit test patterns
1: Evaluate TRAINING_EN bit; 0: ignore TRAINING_EN bit,
captured image readout.
Enable analog output
ADC black reference
Biasing of column load
Biasing of image core
Biasing of first column amplifier
Biasing of the output column amplifier
Biasing of image core
Biasing for column precharge structure
Biasing for analog output amplifier
Biasing of image core
Biasing of y decoder
Biasing of x decoder
Fixed, read only register
Chip revision number
Description
CYIL1SN3000AA
Page 17 of 61
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