CYII4SM014KAA-GEC Cypress Semiconductor Corp, CYII4SM014KAA-GEC Datasheet - Page 11

• Manufacturer Part Number: CYII4SM014KAA-GEC
• Description: SENSOR IMAGE MONO CMOS 49-PGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM014KAA-GEC

• Package / Case: 49-PGA
• Pixel Size: 8µm x 8µm
• Active Pixel Array: 3048H x 4560V
• Frames Per Second: 3
• Voltage - Supply: 3.3V
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: 0 C
• Image Size: 4560 H x 3048 V
• Color Sensing: Monochrome
• Package: 49PGA
• Operating Temperature: 0 to 50 °C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-14000-M; IBIS4-14000-M

Document #: 38-05709 Rev. *C
SYNC_YR is pulsed for the electronic shutter at the appro-
priate moment.
This timing assumes that the registers that control the
subsampling modes have been loaded in advance (through
the SPI interface), before the pulse on SYNC_YL or
SYNC_YR.
The second reset pulse and the pulses on SYL and SYR (all
pulses drawn in red) are only applied when the rolling
electronic shutter is used. For full frame integration, these
pulses are skipped.
The SYNC_Y pulse is also used to initialize the switchboard
(output multiplexer). This is also done by a synchronous reset
on the rising edge of CLK_Y. Normally the switchboard is
controlled by the shift register used for readout (this is the YL
shift register). This means that pin SYNC_Y can be connected
to SYNC_YL, and pin CLK_Y can be connected to CLK_YL.
The additional RESET BLACK pulse (indicated in dashed lines
in
lines black. This can be useful to generate a dark reference
signal.
Timing Pulse Pattern for Readout of a Pixel
Figure 11
register, read out the image row, and analog-digital
conversion. There are 3 tasks:
The SYNC pulses perform a synchronous reset of the shift
registers to the first row/column on a rising edge on CLK. This
is identical for all shift registers (YR, YL and X).
• Preset the X shift register: apply a low level to SYNC_X
• Readout of the image row: pulse CLK_X
• Analog-digital conversion: clock the ADC
Figure 10 on page
during a rising edge on CLK_X at the start of a new row
S Y N C _ X
C L K _ X
A n a lo g
O u tp ut
shows the timing diagram to preset (sync) the X shift
C L K _ A D C
(e xa m p le )
10) can be given to make one or more
T s
Figure 11. Row Readout Timing Sequence
X
T s
Note The SYNC_X signal has a set-up time Ts of 150 ns. For
the YR and YS shift registers, the set-up time is 200 ns. CLK_X
must be stable at least during this set-up time.
In the case where a partial row readout has been performed,
2 CLK_X pulses (with SYNC_X = LOW) are required to fully
deselect the column where the X pointer has been stopped. A
single CLK_X will leave the column partially selected, which
will then have a different response when read out in the next
row. When full row readout has been performed, the last
column will be fully deselected by a single CLK_X pulse (with
SYNC_X = LOW). The X-register is reset by a single CLK_X
pulse (with SYNC_X = LOW). In case of partial row readout,
the SYNC_X pulse has to be given before the sample pulses
(SHR and SHS) of the row sampling process, in order to avoid
a different response of the last column of the previous window.
For the X shift register, the analog signal is delayed by 2 clock
periods before it becomes available at the output (due to
internal processing of the signal in the columns and output
amplifier). The figure gives an example of an ADC clock for an
ADC that samples on the rising edge.
Fast Frame Reset Timing Diagram
Figure 12 on page 12
reset.
SYL and SYR can be kept both high to make the reset
mechanism faster and reduce propagation delays. PC, SHS,
SHR can be kept high since they don’t interact with the pixel
reset mechanism.
Table 5 on page 12
CLK_Y and SELECT.
p ixe l 1
p ixe l 2
lists timing specifications for RESET,
shows the reset timing for a fast frame
CYII4SM014KAA-GEC
CYII4SC014KAA-GTC
p ixe l 3
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