CYII4SM014KAA-GEC Cypress Semiconductor Corp, CYII4SM014KAA-GEC Datasheet - Page 16

• Manufacturer Part Number: CYII4SM014KAA-GEC
• Description: SENSOR IMAGE MONO CMOS 49-PGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM014KAA-GEC

• Package / Case: 49-PGA
• Pixel Size: 8µm x 8µm
• Active Pixel Array: 3048H x 4560V
• Frames Per Second: 3
• Voltage - Supply: 3.3V
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: 0 C
• Image Size: 4560 H x 3048 V
• Color Sensing: Monochrome
• Package: 49PGA
• Operating Temperature: 0 to 50 °C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-14000-M; IBIS4-14000-M

Document #: 38-05709 Rev. *C
Table 8. Pin List (continued)
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Pin #
CLK_YL
VDDR
VDD
GND
GNDAB
SELECT
RESET
CBIAS
PCBIAS
DIN
SCLK
CS
PC
SYNC_X
GND
VDD
CLK_X
SHR
SHS
XBIAS
ABIAS
Name
Power supply for reset line drivers.
Power supply.
Ground.
Anti-blooming reference level (= pin 33).
Control select line of pixel array.
Reset of the selected row of pixels.
Bias current column amplifiers.
Bias current.
Serial data input.
Chip select.
Row initialization pulse.
Sets the X shift register to row 1.
Ground.
Power supply.
Row track & hold reset level
(1 = hold; 0 = track).
Row track & hold signal level (1 = hold;
0 = track).
Bias current X multiplexer.
Bias current pixel array.
Clock of YL shift register.
SPI interface clock.
Clock of YR shift register.
Function
Shifts on rising edge.
Nominal 4V.
Connected on-chip to pin 21.
Nominal 3.3V
0V
Typ. 0V. Set to 1V for improved anti-blooming.
High active. See timing diagrams.
High active. See timing diagrams.
Connect with 22 kΩ to VDD and decouple with 100 nF to
GND.
Connect with 22 kΩ to VDD and decouple with 100 nF to
GND.
16-bit word. LSB first.
Shifts on rising edge.
Data copied to registers on rising edge.
See timing diagrams.
Low active. Synchronous sync on rising edge of CLK_X
150 ns set-up time.
0V
Nominal 3.3V
Shifts on rising edge.
See timing diagram.
See timing diagram.
Connect with 10 kΩ to VDD and decouple with 100 nF to
GND.
Connect with 10 MΩ to VDD and decouple with 100 nF to
GND.
CYII4SM014KAA-GEC
CYII4SC014KAA-GTC
Comment
Page 16 of 27