CYII5FM1300AB-QDC Cypress Semiconductor Corp, CYII5FM1300AB-QDC Datasheet - Page 21
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CYII5FM1300AB-QDC
Manufacturer Part Number
CYII5FM1300AB-QDC
Description
SENSOR IMAGE 1.3MP CMOS 84-LCC
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr
Datasheet
1.CYII5FM1300-EVAL.pdf
(35 pages)
Specifications of CYII5FM1300AB-QDC
Pixel Size
6.7µm x 6.7µm
Active Pixel Array
1280H x 1024V
Frames Per Second
27
Voltage - Supply
3 V ~ 4.5 V
Package / Case
84-LCC
Sensor Image Color Type
Monochrome
Sensor Image Size Range
>= 480,000Pixels
Sensor Image Size
1280x1024Pixels
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 65C
Package Type
CLCC
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package
84CLCC
Image Size
1280x1024 Pixels
Color Sensing
Monochrome
Operating Temperature
0 to 65 °C
Operating Supply Voltage
3 to 3.6 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 20
Global Shutter: Single Slope Integration
SS_START and SS_STOP must change on the falling edge of
the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that
the pulse width of both signals is a minimum of 1 SYS_CLOCK
cycle. As long as SS_START or SS_STOP are asserted, the
sequencer stays in a suspended state (see
T
INT_TIME register is reached. The integration timer is clocked
by the granulated SS-sequencer clock.
T
SS-sequencer clock period.
Document #: 38-05710 Rev. *H
1
2
- Time counted by the integration timer until the value of
- TIME_OUT signal stays high for one granulated
shows a recommended schematic for generating the basic signals and to avoid any timing problems.
Figure 21. Relative Timing of 5-Sequencer Control Signal
Figure 20. .Recommended Schematic for Basic Signals
SYS_CLOCK_N
Figure 22. Global Shutter: Single Slope Integration
Figure
22).
FF
T
signal to trigger the SS_STOP pin (or use an external counter to
trigger SS_STOP); you cannot tie both signals together.
T
signals to reset the image core and start integration. This takes
four granulated SS-sequencer clock periods. The integration
time counter starts counting at the first rising edge after the falling
edge of SS_START.
T
It takes two granulated SS-sequencer clock periods.
T
int
3
4
5
- There are no constraints for this time. Use the TIME_OUT
- The SS-sequencer puts the image core in a readable state.
- During this time, the SS-sequencer applies the control
- The ’real’ integration or exposure time.
SS_START
SS_STOP
Y_CLOCK
Y_START
X_LOAD
SYS_CLOCK
CYII5SM1300AB
Page 21 of 35
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