CYII5SC1300AB-QDC Cypress Semiconductor Corp, CYII5SC1300AB-QDC Datasheet - Page 13
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CYII5SC1300AB-QDC
Manufacturer Part Number
CYII5SC1300AB-QDC
Description
SENSOR IMAGE COLOR CMOS 84-LCC
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr
Specifications of CYII5SC1300AB-QDC
Pixel Size
6.7µm x 6.7µm
Active Pixel Array
1280H x 1024V
Frames Per Second
27
Voltage - Supply
3 V ~ 4.5 V
Package / Case
84-LCC
Sensor Image Color Type
Color
Sensor Image Size Range
>= 480,000Pixels
Sensor Image Size
1280x1024Pixels
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 65C
Package Type
CLCC
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package
84CLCC
Image Size
1280x1024 Pixels
Color Sensing
Color
Operating Temperature
0 to 65 °C
Operating Supply Voltage
3 to 3.6 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Analog to Digital Converter
The IBIS5-B-1300 has a 10-bit flash analog digital converter
running nominally at 40 Msamples/s. The ADC is electrically
separated from the image sensor. Tie the input of the ADC
(ADC_IN; pin 69) externally to the output (PXL_OUT1; pin 28) of
the output amplifier.
Table 14. ADC Specifications
Setting of the ADC Reference Voltages
Figure 14. Internal and External ADC Connections
Document #: 38-05710 Rev. *G
Note
Input range
Quantization
Nominal data rate
DNL (linear conversion
mode)
INL (linear conversion
mode)
Input capacitance
6. The internal ADC range is typically 100 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal resistors
in the ADC.
ADC_VHIGH ~ 2.7V
ADC_VLOW ~ 1.8V
1–3V
10 Bits
40 Msamples/s
Typ. < 0.5 LSB
Typ. < 3 LSB
< 20 pF
[6]
R
ADC
R
R
ADC_VHIGH
external
external
ADC_VLOW
internal
Figure 13. ADC Timing
Table 14. ADC Specifications
ADC Timing
At the rising edge of SYS_CLOCK, the next pixel is fed to the
input of the output amplifier. Due to internal delays of the
SYS_CLOCK signal, it takes approximately 20 ns before the
output amplifier outputs the analog value of the pixel as shown
in
The ADC converts the pixel data on the rising edge of the
ADC_CLOCK, but it takes two clock cycles before this pixel data
is at the output of the ADC.
Due to these delays, it is advisable that a variable phase
difference is foreseen between the ADC_CLOCK and the
SYS_CLOCK to tune the optimal sample moment of the ADC.
The internal resistor R
This results in the following values for the external resistors:
Note that the recommended ADC resistor values yield in a
conversion of the full analog output swing at unity gain
(V
ADC_VLOW).
The values of the resistors depend on the value of R
assure proper working of the ADC, make certain the voltage
difference between ADC_VLOW and ADC_VHIGH is at least
1.0V.
Power dissipation @
40 MHz
Conversion law
R
R
R
ADC_VHIGH
ADC
ADC_VLOW
DARK_ANALOG
Figure
13.
Resistor
<
ADC_VHIGH
ADC
Typ. 45 mA * 3.3V = 150 mW
Linear / Gamma-corrected
has a value of approximately 585Ω.
Figure 13
CYII5SM1300AB
shows this pipeline delay.
and
V
Value (O)
LIGHT_ANALOG
1200
360
585
Page 13 of 34
ADC
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