CYII5SC1300AB-QDC Cypress Semiconductor Corp, CYII5SC1300AB-QDC Datasheet - Page 21

• Manufacturer Part Number: CYII5SC1300AB-QDC
• Description: SENSOR IMAGE COLOR CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AB-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Sensor Image Color Type: Color
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 65C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package: 84CLCC
• Image Size: 1280x1024 Pixels
• Color Sensing: Color
• Operating Temperature: 0 to 65 °C
• Operating Supply Voltage: 3 to 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 20
Global Shutter: Single Slope Integration
SS_START and SS_STOP must change on the falling edge of
the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that
the pulse width of both signals is a minimum of 1 SYS_CLOCK
cycle. As long as SS_START or SS_STOP are asserted, the
sequencer stays in a suspended state. (See
T
INT_TIME register is reached. The integration timer is clocked
by the granulated SS-sequencer clock.
T
SS-sequencer clock period.
Global Shutter: Pixel Readout
Basic Operation
Y_START and Y_CLOCK must change on the falling edge of the
SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that the
pulse width is a minimum of one clock cycle for Y_CLOCK and
three clock cycles for Y_START. As long as Y_CLOCK is applied,
the sequencer stays in a suspended state. (See
Document #: 38-05710 Rev. *G
1
2
—Time counted by the integration timer until the value of
—TIME_OUT
shows a recommended schematic for generating the basic signals and to avoid any timing problems
signal
stays
Figure 20. .Recommended Schematic for Generating Basic Signals
Figure 21. Relative Timing of the 5 Sequencer Control Signal
high
SYS_CLOCK_N
Figure 22. Global Shutter: Single Slope Integration
for
Figure
one
Figure 23
22).
granulated
)
FF
T
signal to trigger the SS_STOP pin (or use an external counter to
trigger SS_STOP); you cannot tie both signals together.
T
signals to reset the image core and start integration. This takes
four granulated SS-sequencer clock periods. The integration
time counter starts counting at the first rising edge after the falling
edge of SS_START.
T
It takes two granulated SS-sequencer clock periods.
T
T
generates the control signals to sample the pixel signal and pixel
reset levels (double sampling fpn-correction), and starts the
readout of one line. The row blanking time depends on the granu-
larity of the X-sequencer clock (see
T
NROF_PIXELS register is reached. PIXEL_VALID goes high
when the internal X_SYNC signal is generated, in other words
when the readout of the pixels is started. PIXEL_VALID goes low
3
4
5
int
1
2
—There are no constraints for this time. Use the TIME_OUT
—During this time, the SS-sequencer applies the control
—The SS-sequencer puts the image core in a readable state.
—Row blanking time: During this period, the X-sequencer
—Pixels counted by pixel counter until the value of
—The ’real’ integration or exposure time.
SS_START
SS_STOP
Y_CLOCK
Y_START
X_LOAD
SYS_CLOCK
Table 21
CYII5SM1300AB
on page 22).
Page 21 of 34