HSP45106JC33 Intersil, HSP45106JC33 Datasheet
HSP45106JC33
Specifications of HSP45106JC33
Related parts for HSP45106JC33
HSP45106JC33 Summary of contents
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... NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ...
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Block Diagram MICROPROCESSOR INTERFACE CLOCK DISCRETE CONTROL SIGNALS Pinouts TICO COS15 COS14 COS13 GND COS12 COS11 COS10 COS9 COS8 COS7 COS6 COS5 COS4 V CC COS3 COS2 COS1 COS0 OEC DACSTRB Pin Descriptions NAME TYPE V +5 power supply pin. ...
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Pin Descriptions (Continued) NAME TYPE ENPHAC I Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENPHAC enables the clocking of data into the Phase Accumulator Register. ENTIREG I Timer Increment ...
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Functional Description The 16-bit Numerically Controlled Oscillator (NCO16) produces a digital complex sinusoid waveform whose frequency and phase are controlled through a standard microprocessor interface and discrete inputs. The NCO16 generates 16-bit sine and cosine vectors at a maximum sample ...
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OES OEC R.ENPHAC 3 TEST PAR/SER BINFMT INPUT SECTION (DISCRETE CONTROL INPUT SIGNALS AND PROCESSOR CONTROL INTERFACE) C(15: PHASE G WR > INPUT REG (16) MOD(2:1) PHEN PHEN G > MSCFEN CS E ...
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Input Section The Input Section loads the data on C(15:0) into one of the seven input registers, the LSB and MSB Center Frequency Input Registers, the LSB and MSB Offset Frequency Registers, the LSB and MSB Timer Input Registers, and ...
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RAMs, using the decoded address bus to select one or the other. The timing for loading the Center Frequency Register (MSB and LSB) and data being output on COS(15:0) and SIN(15:0) is shown in Figure 3. This timing ...
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Phase Offset Adder The output of the Phase Accumulator goes to the Phase Offset Adder, which adds the 16-bit contents of the Phase Offset Register to the 16 MSBs of the phase. Twenty-eight (28) bits of the resulting 32-bit number ...
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ADDRESS SIN/COS / DECODE ARGUMENT BINFMT R.ENPHAC, TEST, PAR/SER OES OEC FIGURE 5. SINE/COSINE SECTION BLOCK DIAGRAM CLK ENPHAC DACSTRB SERIAL DATA OUTPUT FIGURE 6. SERIAL OUTPUT I/O TIMING DIAGRAM CLK CS WRITE WRITE MS INPUT LS INPUT REGISTER ...
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CLK WRITE PHASE INPUT REGISTER WR A(2:0) C(15:0) TRANSFER DATA TO PHASE REGISTER ENPOREG COS(15:0), SIN(15:0) CLK MOD0-2 PMSEL TRANSFER DATA TO PHASE REGISTER ENPOREG COS(15:0), SIN(15:0) FIGURE 9. PHASE MODULATION TO OUTPUT DELAY 10 HSP45106 FIGURE 8. PHASE TO ...
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... Thermal Information = +25°C Thermal Resistance (Typical, Note 1) +0.5V PLCC Package Maximum Junction Temperature PLCC Package +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Die Characteristics Backside Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V SYMBOL TEST CONDITIONS 5.25V IH CC ...
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AC Electrical Specifications V +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER CLK Period CLK High CLK Low WR Period WR High WR Low Setup Time A(2:0 Going High Hold ...
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AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. Waveforms ENABLE/CONTROL SIN(15:0), COS(15:0), TICO (SERIAL MODE ONLY) A(2:0), CS C(15:0) 13 HSP45106 S DUT 1 C (NOTE) L AND I CCSB CCOP EQUIVALENT CIRCUIT t CP ...
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Waveforms (Continued) OES, OEC COS(15:0), SIN(15:0) 14 HSP45106 1.5V 1. 1.7V 1.3V HIGH IMPEDANCE FIGURE 12. OUTPUT ENABLE, DISABLE TIMING 2.0V 2.0V 0.8V 0. FIGURE 13. OUTPUT RISE AND FALL TIMES HIGH IMPEDANCE ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...