HSP45106JC33 Intersil, HSP45106JC33 Datasheet - Page 5
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HSP45106JC33
Manufacturer Part Number
HSP45106JC33
Description
Manufacturer
Intersil
Datasheet
1.HSP45106JC33.pdf
(15 pages)
Specifications of HSP45106JC33
Mounting Style
Surface Mount
Screening Level
Commercial
Lead Free Status / RoHS Status
Not Compliant
OES
OEC
R.ENPHAC
TEST
PAR/SER
BINFMT
C(15:0)
MOD(2:1)
WR
CS
A(2:0)
ENPOREG
ENOFREG
ENCFREG
ENTIREG
ENPHAC
INITPAC
INITTAC
INHOFR
PMSEL
PACI
CLK
D
C
O
D
E
E
>
R
G
E
PHEN
MSCFEN
LSCFEN
MSOFEN
LSOFEN
MSTIEN
LSTIEN
R.PMSEL
R.ENCFREG
R.ENPOREG
R.ENOFREG
R.INHOFR
R.INITPAC
R.PACI
R.ENPHAC
R.ENTIREG
R.INITTAC
3
CLK
INPUT SECTION (DISCRETE CONTROL INPUT SIGNALS
AND PROCESSOR CONTROL INTERFACE)
MSTIEN
WR
WR
WR
LSTIEN
LSOFEN
PHEN
WR
WR
WR
>
>
LSCFEN
>
G
R
E
G
R
E
G
R
E
WR
>
>
>
MSB TIMER INCREMENT
FREQUENCY INPUT
R
E
G
INPUT REG (16)
G
R
E
G
R
E
>
MSB OFFSET
R
G
INPUT REG (16)
E
INCREMENT INPUT
PHASE
INPUT REG (16)
FREQUENCY INPUT
REG (16)
LSB OFFSET
FREQUENCY
INPUT REG (16)
FREQUENCY
LSB TIMER
MSB CENTER
REG (16)
CENTER
REG (16)
LSB
FIGURE 1. BLOCK DIAGRAM OF THE HSP45106
16
16
16
16
16
16
16
20
ENCODER
/
PHASE INPUT
FREQUENCY
ADDRESS
DECODE
CENTER
FREQUENCY
'0'
OFFSET
R.PMSEL
13
3
16
OFFSET FREQUENCY
R.ENCFREG
R.ENOFREG
SIN/COS
CLK
REGISTER
CLK
INCREMENT CLK
32
ROM
R.ENTIREG
32
R.INITTAC
INCREMENT
FREQUENCY
REGISTER
REGISTER
CENTER
TIMER
TIMER
>
>
G
R
E
R.INHOFR
R
G
E
'0'
/
/
16 COS
16 SIN
32
32
32
R.ENPOREG
CLK
>
PHASE OFFSET
R
E
G
16
REGISTER
FREQUENCY
32
CONTROL
32
>
ADDER
R.INITTAC
FORMAT
'0'
R
E
G
32
32
A
D
D
E
R
R.INITPAC
'0'
32
32
28
MSBs
16
/
16
PHASE OFFSET
32
32
ACCUMULATOR
CONTROL
R.PACI
OUTPUT
ADDER
R.ENPHAC
32
A
D
D
E
R
32
SECTION
A
D
D
E
R
TIMER
A
D
D
E
R
LSBs
CLK
32
CLK
SIN/COS ARGUMENT
16
/
/
ACCUMULATOR
ACCUMULATOR
16
16
CLK
16
>
32
REGISTER
G
R
E
SECTION
CLK
PHASE
PHASE
>
G
R
E
>
32
R
E
G
>
SIN(15:0)
COS(15:0)
DACSTRB
32
R
G
E
28
TICO