HSP45106JC33 Intersil, HSP45106JC33 Datasheet - Page 12

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HSP45106JC33

Manufacturer Part Number
HSP45106JC33
Description
Manufacturer
Intersil
Datasheet

Specifications of HSP45106JC33

Mounting Style
Surface Mount
Screening Level
Commercial
Lead Free Status / RoHS Status
Not Compliant
AC Electrical Specifications
NOTES:
CLK Period
CLK High
CLK Low
WR Period
WR High
WR Low
Setup Time A(2:0), CS to WR Going High
Hold Time A(2:0), CS from WR Going High
Setup Time C(15:0) to WR Going High
Hold Time C(15:0) from WR Going High
Setup Time WR High to CLK High
Setup Time MOD(2:0) to CLK Going High
Hold Time MOD(2:0) from CLK Going High
Setup Time ENPOREG, ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC,
BINFMT, TEST, PAR / SER, PACI, INITTAC
to CLK Going High
Hold Time ENPOREG, ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC,
BINFMT, TEST, PAR / SER, PACI, INITTAC
from CLK Going High
CLK to Output Delay SIN(15:0), COS(15:0), TICO
CLK to Output Delay DACSTRB
Output Enable Time
Output Disable Time
Output Rise, Fall Time
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK)
6. If ENOFREG, ENCFREG, ENTIREG, or ENPOREG are active, care must be taken to not violate setup and hold times to these registers when
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
2.0V; all others 1.5V. Output load per test load circuit with switch closed and C
< 1.5V.
writing data into the chip via the C(15:0) port.
PARAMETER
12
V
+25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
CC
= 5.0V ±5%, T
A
SYMBOL
= 0
t
t
t
t
t
t
t
t
t
t
AWH
CWS
CWH
t
MCH
t
t
AWS
MCS
ECH
t
DSO
t
t
t
ECS
t
t
t
WP
WH
WC
CH
WL
DO
OE
OD
HSP45106
°
CP
CL
RF
C to +70
°
C (Note 5). Parameters with MIN and/or MAX limits are 100% tested at
(Note 6)
(Note 7)
(Note 7)
NOTES
L
= 40pF. Output transition is measured at V
MIN
39
15
15
39
15
15
13
15
16
15
12
1
0
0
0
2
-
-
-
-
25.6MHz
MAX
18
18
12
15
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MIN
30
12
12
30
12
12
13
15
12
15
12
1
0
0
0
2
-
-
-
-
33MHz
MAX
15
15
12
15
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OH
> 1.5V and V
October 16, 2008
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FN2809.8
OL

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