TDA7330BD STMicroelectronics, TDA7330BD Datasheet - Page 4
TDA7330BD
Manufacturer Part Number
TDA7330BD
Description
Audio DSPs RDS Demodulator
Manufacturer
STMicroelectronics
Datasheet
1.TDA7330BD.pdf
(9 pages)
Specifications of TDA7330BD
Mounting Style
SMD/SMT
Package / Case
SO-20
Pin Count
20
Screening Level
Industrial
Package Type
SO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TDA7330B
ELECTRICAL CHARACTERISTICS (continued)
Note(2): The 3th harmonic (57KHz) must be less than -40dB in respect to the input signal 19KHz plus gain.
Figure 2: RDS timing diagram
OUTPUT TIMING
The generated 1187.5Hz output clock (RDCL
line) is synchronized to the incoming data.
According to the internal PLL lock condition this
Figure 3: Test Circuit
4/9
Measure
A
B
C
f1 (KHz)
56.5
55.5
56
f2 (KHz)
57
57
57
f3 (KHz)
57.5
58.5
58
Ph max
<7.5
<10
<5
data change can results on the falling or on the
rising clock edge.
Whichever clock edge is used by the decoder (ris-
ing or falling edge) the data will remain valid for
416.7 sec after the clock transition.