ispPAC-CLK5304S-01TN48I Lattice, ispPAC-CLK5304S-01TN48I Datasheet - Page 20

• Manufacturer Part Number: ispPAC-CLK5304S-01TN48I
• Description: Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ispPAC-CLK5304S-01TN48I

• Max Input Freq: 267 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 13. Reference and Feedback Input
Each input features internal programmable termination resistors as shown in Figure 14. The REFA and REFB
inputs terminate to VTT_REFA and VTT_REFB respectively. In order to interface to differential clock input one
should connect VTT_REFA and VTT_REFB pins together on circuit board and if necessary connect the common
node to VTT supply.
The direct connection from REFA and REFB pins to the output routing matrix becomes unavailable when the REFA
and REFB pins are configured as differential input pins.
• eHSTL
• Differential SSTL1.8
• Differential SSTL2
• Differential SSTL3
• Differential HSTL
• LVDS
• LVPECL (differential, 3.3V)
REFA_REFP
REFB_REFN
VTT_FBK
REFSEL
FBK
+
–
0
1
20
ispClock5300S Family Data Sheet
INTERNAL
FEEDBACK
TO OUTPUT
DETECT
PHASE
FREQ.
ROUTING
MATRIX