ispPAC-CLK5304S-01TN48I Lattice, ispPAC-CLK5304S-01TN48I Datasheet - Page 23

• Manufacturer Part Number: ispPAC-CLK5304S-01TN48I
• Description: Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ispPAC-CLK5304S-01TN48I

• Max Input Freq: 267 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 17. LVDS Input Receiver Configuration
Note that while a floating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry
may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-
put driver typically requires an external DC ‘pull-down’ path to a V
properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5300S inter-
nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive
current. The pull-down should be implemented with external resistors placed close to the LVPECL driver
(Figure 18)
Figure 18. LVPECL Input Receiver Configuration
Please note that while the above discussions specify using 50Ω termination impedances, the actual impedance
required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The
Driver
LVPECL
Driver
LVDS
R
PD
V
TERM
REFA_REFP
REFB_REFN
VTT_REFB
VTT_REFA
R
PD
REFA_REFP
REFB_REFN
REFB-VTT
REFA-VTT
23
Close
50
50
Close
ispClock5300S
Differential
Receiver
+
–
TERM
Close
50
Close
50
ispClock5300S
ispClock5300S Family Data Sheet
Differential
termination voltage (typically VCC-2V) to
Receiver
+
–