DS3102GN Maxim Integrated Products, DS3102GN Datasheet
DS3102GN
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DS3102GN Summary of contents
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... Ordering Information PART TEMP RANGE DS3102GN -40C to +85C DS3102GN+ -40C to +85C +Denotes a lead(Pb)-free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’ ...
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DS3102 1. STANDARDS COMPLIANCE ..........................................................................................................6 2. APPLICATION EXAMPLE ...............................................................................................................7 3. BLOCK DIAGRAM ...........................................................................................................................8 4. DETAILED DESCRIPTION ..............................................................................................................9 5. DETAILED FEATURES .................................................................................................................11 5 NPUT LOCK EATURES 5.2 T0 DPLL F ......................................................................................................................11 EATURES 5.3 T4 DPLL F ......................................................................................................................11 ...
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DS3102 7 QUIPMENT EDUNDANCY 7.9.1 Master-Slave Output Clock-Phase Alignment ..................................................................................... 46 7.9.2 Master-Slave Frame and Multiframe Alignment with the External Frame-Sync Signals ..................... 47 7.9.3 SYNCn Pins ......................................................................................................................................... 49 7.9.4 Other Configuration Options ................................................................................................................ 50 7.10 M ...
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DS3102 Figure 2-1. Typical Application Example ..................................................................................................................... 7 Figure 3-1. Block Diagram ........................................................................................................................................... 8 Figure 7-1. DPLL Block Diagram ............................................................................................................................... 26 Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 28 Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 31 ...
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DS3102 Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14 Table 6-3. Global Pin Descriptions ............................................................................................................................ 15 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15 Table ...
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DS3102 1. Standards Compliance Table 1-1. Applicable Telecom Standards SPECIFICATION ANSI T1.101 Synchronization Interface Standard, 1999 TIA/EIA-644-A Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001 ETSI Transmission and Multiplexing (TM); Generic requirements of transport functionality of ...
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DS3102 2. Application Example Figure 2-1. Typical Application Example Backplane <0> typically 19.44 MHz point-to-point or multidrop buses <0> <1> <1> <1> <1> divide line clock down to backplane rate, send to timing cards <N> <N> <N> <N> select ...
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DS3102 3. Block Diagram Figure 3-1. Block Diagram IC1 POS/NEG IC2 POS/NEG IC3 IC4 IC5 POS/NEG IC6 POS/NEG IC8 IC9 SYNC1 SYNC2 SYNC3 JTRST JTMS JTAG JTCLK JTDI JTDO See Figure 7-1 for a detailed view of the T0 ...
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DS3102 4. Detailed Description Figure 3-1 illustrates the blocks described in this section and how they relate to one another. Section detailed feature list. The DS3102 is a highly integrated timing card IC for systems with SONET/SDH or Synchronous ...
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DS3102 The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus, the free-run and holdover stability of the DS3102-based timing card is entirely a function of the stability of the external oscillator, the performance ...
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DS3102 5. Detailed Features 5.1 Input Clock Features Eight input clocks: four CMOS/TTL (≤ 125MHz) and four LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz) CMOS/TTL input clocks accept any multiple of 2kHz up to 125MHz LVDS/LVPECL inputs accept any multiple ...
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DS3102 5.4 Output APLL Features Three separate clock multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates, Fast/Gigabit Ethernet rates, and 10G Ethernet rates, all locked to a common reference clock The T0 APLL, always connected to ...
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DS3102 6. Pin Descriptions Table 6-1. Input Clock Pin Descriptions (1) (2) PIN NAME TYPE Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local REFCLK I oscillator (TCXO, OCXO, or XO). See Section 7.3. Input Clock 1. LVDS/LVPECL ...
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DS3102 Table 6-2. Output Clock Pin Descriptions (1) (2) PIN NAME TYPE OC1 O Output Clock 1. CMOS/TTL. Programmable frequency (default 6.48MHz). OC2 O Output Clock 2. CMOS/TTL. Programmable frequency (default 38.88MHz). OC3 O Output Clock 3. CMOS/TTL. Programmable ...
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DS3102 Table 6-3. Global Pin Descriptions (1) (2) PIN NAME TYPE Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as ...
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DS3102 Table 6-5. JTAG Interface Pin Descriptions See Section 9 for functional description and Section (1) (2) PIN NAME TYPE JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If JTRST I PU not used, ...
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DS3102 7. Functional Description 7.1 Overview The DS3102 has eight input clocks pins and three frame-sync input pins. The device can output as many as nine different clock frequencies on 16 output clock pins. There are two separate DPLLs ...
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DS3102 Typically, the internal state machine controls the T0 DPLL, but manual control by system software is also available. The T4 DPLL has a simpler state machine that software cannot directly control. In either DPLL, however, software can override ...
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DS3102 00h to indicate the failure. In response to the activation of the INTREQ pin or during periodic polling, if system software ever reads 00h from the that the local oscillator attached to that DS3102 has failed. For proper ...
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DS3102 7.4.2 Frequency Configuration Input clock frequencies are configured in the FREQ field of the same registers specify the locking frequency mode, as shown in Table 7-3. Locking Frequency Modes LOCKING FREQUENCY DIVN LOCK8K 0 0 Direct Lock 0 ...
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DS3102 7.5 Input Clock Monitoring Each input clock is continuously monitored for frequency accuracy and activity. Frequency monitoring is desribed in Section 7.5.1, while activity monitoring is described in Sections frequency out-of-band alarm or activity alarm is automatically declared ...
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DS3102 decrements if no irregularities occur. Thus the “leak” rate of the bucket is approximately units/second. A leak is prevented when a fill event occurs in the same interval. When the value of an ...
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DS3102 7.6 Input Clock Priority, Selection, and Switching 7.6.1 Priority Configuration During normal operation, the selected reference for the T0 DPLL and the selected reference for the T4 DPLL are chosen automatically based on the priority rankings assigned to ...
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DS3102 In nonrevertive mode, planned switchover to a newly valid higher priority input clock can be done manually under software control. The validation of the new higher priority clock sets the corresponding status bit in the MSR2 register, which ...
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DS3102 In external reference switching mode the device is simply a clock switch, and the T0 DPLL is forced to lock onto the selected reference whether it is valid. Unlike forced reference selection (Section 7.6.3) this mode controls the ...
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DS3102 7.7 DPLL Architecture and Configuration Both T0 and T4 are digital PLLs with separate analog PLLs (APLLs) as the output stage. This architecture combines the benefits of both PLL types. See Figure 7-1. DPLL Block Diagram T4 T4 ...
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DS3102 Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations, temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers. DPLLs use digital frequency synthesis (DFS) to ...
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DS3102 Figure 7-2. T0 DPLL State Transition Diagram (selected reference invalid > 2s [selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher priority input)] AND valid input clock available [selected reference invalid OR (revertive ...
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DS3102 7.7.1.3 Locked State The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.6). ...
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DS3102 DPLL when it was in the locked state. The device can be configured for manual or automatic holdover as described in the following subsections. When at least one input clock has been declared valid, the state machine immediately ...
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DS3102 Figure 7-3. T4 DPLL State Transition Diagram SELECTED REFERENCE SWITCH SELECTED REFERENCE PHASE-LOCKED > 2s SELECTED REFERENCE SWITCH PRELOCKED 2 19-4617; Rev 5; 8/10 RESET FREE-RUN SELECTED REFERENCE SELECTED REFERENCE ACTIVE INACTIVE > 2s PRELOCKED PHASE-LOCKED TO SELECTED ...
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DS3102 7.7.3 Bandwidth The bandwidth of the T4 DPLL is configured in the The bandwidth of the T0 DPLL is configured in the 400Hz. The AUTOBW bit in the MCR9 T0 DPLL uses the T0ABW bandwidth during acquisition (not ...
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DS3102 The T0 DPLL phase detectors can be configured for normal phase/frequency locking (360 capture) or nearest edge phase locking (180 capture). With nearest edge detection the phase detectors are immune to occasional missing clock cycles. The DPLL automatically ...
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DS3102 When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the T4LOCK bit in the MSR3 register and requests an interrupt if enabled. 7.7.7 Phase Build-Out 7.7.7.1 Phase Monitor The T0 DPLL has a phase monitor ...
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DS3102 7.7.7.4 PBO Phase Offset Adjustment An uncertainty 5ns is introduced each time a phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large number of phase build-out events ...
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DS3102 For the T0 DPLL the PHASE field always indicates the phase difference between the selected reference and the internal feedback clock. The T4 DPLL, however, can be configured to measure the phase difference between two input clocks. When ...
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DS3102 Table 7-6. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode LOCKING MODE LOCKING FOR T4 MODE FOR T0 SELECTED SELECTED REFERENCE REFERENCE LOCK8K or DIRECT DIVN(8K) LOCK8K or LOCK8K DIVN(8K) LOCK8K or DIVN (8K) DIVN(8K) LOCK8K ...
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DS3102 7.7.13 Output Jitter and Wander Several factors contribute to jitter and wander on the output clocks, including: Jitter and wander amplitude on the selected reference (while in the locked state) The jitter/wander transfer characteristic of the ...
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DS3102 7.8.1 Signal Format Configuration Output clocks OC4, OC5, OC6, and OC7 are LVDS-compatible, LVPECL level-compatible outputs. The type of output can be selected or the output can be disabled using the OCnSF configuration bits in the LVPECL level-compatible ...
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DS3102 DIG2F[1:0] field in MCR7. DIG1 and DIG2 can be independently configured for any of the frequencies shown in Table 7-8 and Table 7-9, respectively. The APLL DFS blocks and their associated output APLLs and output dividers can generate ...
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DS3102 Table 7-9. Digital2 Frequencies DIG2AF DIG2F[1:0] DIG2SS SETTING SETTING SETTING IN MCR6 IN MCR7 IN MCR6 ...
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DS3102 Table 7-13. T4 APLL Frequency Configuration T4 APLL T4 APLL DFS FREQUENCY FREQUENCY (MHz) (MHz) Disabled 77.76 311.04 77.76 98.304 24.576 131.072 32.768 148.224 37.056 98.816 24.704 274.944 68.736 178.944 44.736 100.992 25.248 250.000 62.500 122.88 30.720 160.000 ...
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DS3102 Table 7-15. Standard Frequencies for Programmable Outputs FREQUENCY (MHz) 2kHz 8kHz Not OC4, OC5 from T4 APLL 1.536 Not OC4 to OC7 from T0 APLL 1.544 Not OC6 from DIG2 Not OC4, OC5 from T4 APLL 1.544 Not ...
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DS3102 FREQUENCY (MHz) 15.552 OC1–OC3 only 16.000 Not OC6, OC7 16.384 Not OC6 from DIG2 16.384 16.384 16.832 17.184 18.528 19.440 Not OC6 19.440 20.000 20.800 OC2, OC3, OC6, OC7 only 22.368 24.576 24.576 OC2, OC3, OC6, OC7 only ...
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DS3102 FREQUENCY (MHz) OC6, OC7 only from T4 APLL 104.000 OC6, OC7 only 122.880 OC6, OC7 only Not OC1–OC3 from T0 APLL 125.000 Not OC1, OC2 from T4 APLL Not OC1–OC3 from T0 APLL 131.072 OC6, OC7 only from ...
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DS3102 7.8.2.5 Custom Output Frequencies In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz ...
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DS3102 Given this information, if master and slave devices are crosswired with 19.44MHz clocks, for example, the output clocks 19.44MHz ( 16) from the two devices are phase-aligned with one ...
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DS3102 Table 7-17. External Frame-Sync Mode and Source T0 DPLL MCR3: FSCR3: 1 LOCKED EFSEN SOURCE XXXX 1 0 XXXX 1 1 <>11XX 1 1 <>11XX 1 1 11XX Note 1: That is, when OPSTATE:T0STATE= 100. ...
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DS3102 generator is not synchronized with the FSYNC/MFSYNC 2kHz alignment generator and continues to free-run with its existing 2kHz alignment. This avoids any disturbance on the T0 DPLL derived output clocks when SYNCn has a change of phase position. ...
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DS3102 7.9.4 Other Configuration Options FSYNC and MFSYNC are always produced from the T0 DPLL. Output clocks OC1 to OC7 can also be configured as 2kHz or 8kHz outputs, derived from either the T0 DPLL or the T4 DPLL ...
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DS3102 increment its address counter, and prefetch the following byte. After the address counter reaches 3FFFh, it rolls over to address 0000h and continues to increment. Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions ...
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DS3102 Figure 7-6. SPI Bus Transactions Single-Byte Write CS R/W Register Address Burst SDI 0 (Write) SDO Single-Byte Read CS R/W Register Address Burst SDI 1 (Read) SDO Burst Write CS R/W Register Address Burst Data Byte 1 SDI ...
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DS3102 7.11 Reset Logic The device has three reset controls: the RST pin, the RST bit in MCR1, and the JTAG reset pin JTRST. The RST pin asynchronously resets the entire device, except for the JTAG logic. When the ...
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DS3102 8. Register Descriptions The DS3102 has an overall address range from 000h to 1FFh. each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are reserved and ...
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DS3102 8.4 Register Definitions Table 8-1. Register Map Note: Register names are hyperlinks to register definitions. Underlined fields are read-only. ADDR REGISTER BIT 7 00h ID1 01h ID2 02h REV 03h TEST1 PALARM 05h MSR1 IC8 06h MSR2 STATE ...
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DS3102 ADDR REGISTER BIT 7 3Ah MCR8 OC5SF 3Bh MCR9 AUTOBW 3Ch MCLK1 3Dh MCLK2 3Eh HOCR1 3Fh HOCR2 40h HOCR3 AVG 41h DLIMIT1 42h DLIMIT2 — 43h IER1 IC8 44h IER2 STATE SRFAIL 45h IER3 FSMON T4LOCK 46h ...
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DS3102 ADDR REGISTER BIT 7 6Dh T0CR3 PD2EN 6Eh GPCR GPIO4D GPIO3D 6Fh GPSR — 70h OFFSET1 71h OFFSET2 72h PBOFF — 73h PHLIM1 FLEN 74h PHLIM2 CLEN MCPDEN USEMCPD 76h PHMON NW 77h PHASE1 78h PHASE2 79h PHLKTO ...
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DS3102 Register Name: ID1 Register Description: Device Identification Register, LSB Register Address: 00h Bit # 7 6 Name Default 0 0 Bits Device ID (ID[7:0]). ID[15:0] = 0C1Eh = 3102 decimal. Register Name: ID2 Register Description: ...
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DS3102 Register Name: TEST1 Register Description: Test Register 1 (Not Normally Used) Register Address: 03h Bit # 7 6 Name PALARM D180 Default 0 0 Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the ...
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DS3102 Register Name: MSR1 Register Description: Master Status Register 1 Register Address: 05h Bit # 7 6 Name IC8 — Default 1 0 Bits 7 and Input Clock Status Change (IC8 and IC[6:1]). Each of these ...
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DS3102 Register Name: FREQ3 Register Description: Frequency Register 3 Register Address: 07h Bit # 7 6 Name — — Default 0 0 Bits Current DPLL Frequency (FREQ[18:16]). See the Register Name: MSR3 Register Description: Master Status ...
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DS3102 Register Name: OPSTATE Register Description: Operating State Register Register Address: 09h Bit # 7 6 Name FSMON T4LOCK Default 1 0 Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This real-time status bit indicates the current status of the ...
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DS3102 Register Name: PTAB1 Register Description: Priority Table Register 1 Register Address: 0Ah Bit # 7 6 Name Default 0 0 Bits Highest Priority Valid Reference (REF1[3:0]). This real-time status field indicates the highest priority valid ...
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DS3102 Register Name: PTAB2 Register Description: Priority Table Register 2 Register Address: 0Bh Bit # 7 6 Name Default 0 0 Bits Third Highest Priority Valid Reference (REF3[3:0]). This real-time status field indicates the third highest ...
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DS3102 Register Name: FREQ1 Register Description: Frequency Register 1 Register Address: 0Ch Bit # 7 6 Name Default 0 0 Note: The FREQ1, FREQ2, and FREQ3 registers must be read consecutively. See Section 8.3. Bits Current ...
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DS3102 Register Name: VALSR1 Register Description: Input Clock Valid Status Register 1 Register Address: 0Eh Bit # 7 6 Name IC8 — Default 0 0 Bits 7 and Input Clock Valid Status (IC8 and IC[6:1]). Each ...
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DS3102 Register Name: ISR1 Register Description: Input Status Register 1 Register Address: 10h Bit # 7 6 Name SOFT2 HARD2 Default 0 1 Bit 7: Soft Frequency Limit Alarm for Input Clock 2 (SOFT2). This real-time status bit indicates ...
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DS3102 Register Name: ISR2 Register Description: Input Status Register 2 Register Address: 11h Bit # 7 6 Name SOFT4 HARD4 Default 0 1 Bit 7: Soft Frequency Limit Alarm for Input Clock 4 (SOFT4). This real-time status bit indicates ...
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DS3102 Register Name: ISR3 Register Description: Input Status Register 3 Register Address: 12h Bit # 7 6 Name SOFT6 HARD6 Default 0 1 This register has the same behavior as the ISR1and Register Name: ISR4 Register Description: Input Status ...
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DS3102 Register Name: MSR4 Register Description: Master Status Register 4 Register Address: 17h Bit # 7 6 Name FHORDY SHORDY Default 0 0 Bit 7: Fast Holdover Frequency Ready (FHORDY). This latched status bit is set to 1 when ...
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DS3102 Register Name: IPR1 Register Description: Input Priority Register 1 Register Address: 18h Bit # 7 Name Default (T0) 0 Default (T4) 0 Bits Priority for Input Clock 2 (PRI2[3:0]). Priority 0001 is highest; priority 1111 ...
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DS3102 Register Name: IPR3 Register Description: Input Priority Register 3 Register Address: 1Ah Bit # 7 Name Default (T0) 0 Default (T4) 0 These registers have the same behavior as Register Name: IPR4 Register Description: Input Priority Register 4 ...
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DS3102 Register Name: ICR1, ICR2, ICR3, ICR4, ICR5, ICR6, ICR8, ICR9 Register Description: Input Configuration Register Register Address: 20h, 21h, 22h, 23h, 24h, 25h, 27h, 28h Bit # 7 6 Name ...
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DS3102 DIVN = 1 and LOCK8K = 1: (Alternate direct-lock frequency decode) 0000 = 10MHz (internally divided down to 5MHz) 0001 = 25MHz (internally divided down to 5MHz) 0010 = 62.5MHz (internally down to 31.25MHz) 0011 = 125MHz (internally ...
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DS3102 Register Name: MCR1 Register Description: Master Configuration Register 1 Register Address: 32h Bit # 7 6 Name RST — Default 0 0 Bit 7: Device Reset (RST). When this bit is high the entire device is held in ...
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DS3102 Register Name: MCR2 Register Description: Master Configuration Register 2 Register Address: 33h Bit # 7 6 Name — — Default 0 0 Bits DPLL Force Selected Reference (T0FORCE[3:0]). This field provides a way to ...
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DS3102 Register Name: MCR3 Register Description: Master Configuration Register 3 Register Address: 34h Bit # 7 6 Name AEFSEN LKATO Default 1 1 Bit 7: Auto External Frame Sync Enable (AEFSEN). This bit has two functions depending on the ...
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DS3102 Register Name: MCR4 Register Description: Master Configuration Register 4 Register Address: 35h Bit # 7 6 Name LKT4T0 — Default 0 0 Bit 7: Lock (LKT4T0). When this bit is set to 1 (and T0CR1:T4APT0 ...
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DS3102 Register Name: MCR5 Register Description: Master Configuration Register 5 Register Address: 36h Bit # 7 6 Name Default 0 0 Bits Reserved Bits (RSV[4:1]). These bits are reserved for future use. They ...
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DS3102 Register Name: OCR6 Register Description: Output Configuration Register 6 Register Address: 37h Bit # 7 6 Name — OC5EN Default 0 1 Bit 6: OC5 Output Enable (OC5EN). Enables the OC5 output pin Output clock pin ...
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DS3102 Register Name: MCR6 Register Description: Master Configuration Register 6 Register Address: 38h Bit # 7 6 Name DIG2AF DIG2SS Default 0 see below Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies Digital2 ...
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DS3102 Register Name: MCR7 Register Description: Master Configuration Register 7 Register Address: 39h Bit # 7 6 Name DIG2F[1:0] Default 0 0 Bits 7 and 6: Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS, and MCR6:DIG2AF configure the frequency of the ...
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DS3102 Register Name: MCR8 Register Description: Master Configuration Register 8 Register Address: 3Ah Bit # 7 6 Name OC5SF[1:0] Default 1 0 For rev A2 devices, in LVPECL mode the differential output voltage is higher than the max V ...
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DS3102 Register Name: MCR9 Register Description: Master Configuration Register 9 Register Address: 3Bh Bit # 7 6 Name AUTOBW — Default 1 1 Bit 7: Automatic Bandwidth Selection (AUTOBW). See Section 7.7. Always selects locked bandwidth from ...
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DS3102 Register Name: MCLK1 Register Description: Master Clock Frequency Adjustment Register 1 Register Address: 3Ch Bit # 7 6 Name Default 1 0 Note: The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See Section 8.3. ...
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DS3102 Register Name: HOCR1 Register Description: Holdover Configuration Register 1 Register Address: 3Eh Bit # 7 6 Name Default 0 0 Bits Holdover Frequency (HOFREQ[7:0]). The full 19-bit HOFREQ[18:0] field spans this register, and HOCR3. HOFREQ ...
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DS3102 Register Name: HOCR3 Register Description: Holdover Configuration Register 3 Register Address: 40h Bit # 7 6 Name AVG FAST Default 1 0 Note: See Section 8.3 for important information about writing and reading this register. Bit 7: Averaging ...
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DS3102 Register Name: DLIMIT1 Register Description: DPLL Frequency Limit Register 1 Register Address: 41h Bit # 7 6 Name Default 0 1 Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3. Bits ...
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DS3102 Register Name: IER1 Register Description: Interrupt Enable Register 1 Register Address: 43h Bit # 7 6 Name IC8 — Default 0 0 Bits 7 and Interrupt Enable for Input Clock Status Change (IC8 and IC[6:1]). ...
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DS3102 Register Name: IER3 Register Description: Interrupt Enable Register 3 Register Address: 45h Bit # 7 6 Name FSMON T4LOCK Default 0 0 Bit 7: Interrupt Enable for Frame-Sync Input Monitor Alarm (FSMON). This bit is an interrupt enable ...
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DS3102 Register Name: DIVN1 Register Description: DIVN Register 1 Register Address: 46h Bit # 7 6 Name Default 1 1 Note: The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See Section 8.3. Bits 7 to ...
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DS3102 Register Name: MCR10 Register Description: Master Configuration Register 10 Register Address: 48h Bit # 7 6 Name FMONCLK SRFPIN Default 0 0 Bit 7: Frequency Monitor Clock Source (FMONCLK). This bit specifies the clock source for the input ...
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DS3102 Register Name: ILIMIT Register Description: Input Clock Frequency Limit Register Register Address: 49h Bit # 7 6 Name SOFT[3:0] Default 0 0 Bits Soft Frequency Alarm Limit (SOFT[3:0]). This field is an unsigned integer that ...
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DS3102 Register Name: MCR11 Register Description: Master Configuration Register 11 Register Address: 4Bh Bit # 7 6 Name — — Default 0 0 Bit Path Select (T4T0). This bit specifies which path is being accessed ...
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DS3102 Register Name: DLIMIT3 Register Description: DPLL Frequency Limit Register 3 Register Address: 4Dh Bit # 7 6 Name FLLOL Default 1 0 Bit 7: Frequency Limit Loss-of-Lock (FLLOL). When this bit is set to 1, the T0 DPLL ...
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DS3102 Register Name: OCR5 Register Description: Output Configuration Register 1 Register Address: 4Fh Bit # 7 6 Name — AOF7 Default 0 0 Bit 6: Alternate Output Frequency Mode Select 7 (AOF7). This bit controls the decoding of the ...
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DS3102 Register Name: LB0U Register Description: Leaky Bucket 0 Upper Threshold Register Register Address: 50h Bit # 7 6 Name Default 0 0 Bits Leaky Bucket 0 Upper Threshold (LB0U[7:0]). When the leaky bucket accumulator is ...
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DS3102 Register Name: LB1U, LB2U, LB3U Register Description: Leaky Bucket 1/2/3 Upper Threshold Register Register Address: 54h, 58h, 5Ch Bit # 7 6 Name Default 0 0 Bits Leaky Bucket “x” Upper Threshold (LBxU[7:0]). See the ...
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DS3102 Register Name: OCR1 Register Description: Output Configuration Register 1 Register Address: 60h Bit # 7 6 Name OFREQ2[3:0] Default 1 0 Bits Output Frequency of OC2 (OFREQ2[3:0]). This field specifies the frequency of output clock ...
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DS3102 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided ...
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DS3102 Register Name: OCR2 Register Description: Output Configuration Register 2 Register Address: 61h Bit # 7 6 Name OFREQ4[3:0] Default 1 0 Bits Output Frequency of OC4 (OFREQ4[3:0]). This field specifies the frequency of output clock ...
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DS3102 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided ...
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DS3102 Register Name: OCR3 Register Description: Output Configuration Register 3 Register Address: 62h Bit # 7 6 Name OFREQ6[3:0] Default 1 0 Bits Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock ...
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DS3102 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 2 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided ...
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DS3102 Register Name: OCR4 Register Description: Output Configuration Register 4 Register Address: 63h Bit # 7 6 Name MFSEN FSEN Default 1 1 Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFSYNC pin. ...
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DS3102 Register Name: T4CR1 Register Description: T4 DPLL Configuration Register 1 Register Address: 64h Bit # 7 6 Name — — Default 0 0 Bits APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0 = 0, the T4 APLL ...
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DS3102 Register Name: T0CR1 Register Description: T0 DPLL Configuration Register 1 Register Address: 65h Bit # 7 6 Name T4MT0 T4APT0 Default 0 0 Bit 7: T4 Measure T0 Phase (T4MT0). When this bit is set to 1 the ...
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DS3102 Register Name: T4BW Register Description: T4 Bandwidth Register Register Address: 66h Bit # 7 6 Name 0 0 Default 0 0 Bits DPLL Bandwidth (T4BW[2:0]). See Section 7.7. 18Hz 01 = 35Hz ...
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DS3102 Register Name: T0ABW Register Description: T0 DPLL Acquisition Bandwidth Register Register Address: 69h Bit # 7 6 Name — — Default 0 0 Bits DPLL Acquisition Bandwidth (T0ABW[4:0]). This field configures the bandwidth of ...
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DS3102 Register Name: T4CR2 Register Description: T4 Configuration Register 2 Register Address: 6Ah Bit # 7 6 Name — Default 0 0 Bits Phase Detector 2 Gain 8kHz (PD2GA8K[2:0]). This field specifies the gain of the ...
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DS3102 Register Name: T0CR2 Register Description: T0 Configuration Register 2 Register Address: 6Bh Bit # 7 6 Name — Default 0 0 Bits Phase Detector 2 Gain, 8kHz (PD2G8K[2:0]). This field specifies the gain of the ...
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DS3102 Register Name: T4CR3 Register Description: T4 Configuration Register 3 Register Address: 6Ch Bit # 7 6 Name PD2EN — Default 1 1 Bit 7: Phase Detector 2 Gain Enable (PD2EN). When this bit is set to 1, the ...
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DS3102 Register Name: GPCR Register Description: GPIO Configuration Register Register Address: 6Eh Bit # 7 6 Name GPIO4D GPIO3D Default 0 0 Bit 7: GPIO4 Direction (GPIO4D). This bit configures the data direction for the GPIO4 pin. When GPIO4 ...
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DS3102 Register Name: GPSR Register Description: GPIO Status Register Register Address: 6Fh Bit # 7 6 Name — — Default 0 0 Bit 3: GPIO4 State (GPIO4). This bit indicates the current state of the GPIO4 pin ...
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DS3102 Register Name: OFFSET1 Register Description: Phase Offset Register 1 Register Address: 70h Bit # 7 6 Name Default 0 0 Note: The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See Section 8.3. Bits 7 ...
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DS3102 Register Name: PBOFF Register Description: Phase Build-Out Offset Register Register Address: 72h Bit # 7 6 Name — — Default 0 0 Bits Phase Build-Out Offset Register (PBOFF[5:0]). An uncertainty 5ns is ...
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DS3102 Register Name: PHLIM2 Register Description: Phase Limit Register 2 Register Address: 74h Bit # 7 6 Name CLEN MCPDEN Default 1 0 Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified ...
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DS3102 Register Name: PHMON Register Description: Phase Monitor Register Register Address: 76h Bit # 7 6 Name NW — Default 0 0 Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration ...
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DS3102 Register Name: PHASE1 Register Description: Phase Register 1 Register Address: 77h Bit # 7 6 Name Default 0 0 Note: The PHASE1 and PHASE2 registers must be read consecutively. See Section 8.3. Bits Current DPLL ...
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DS3102 Register Name: FSCR1 Register Description: Frame-Sync Configuration Register 1 Register Address: 7Ah Bit # 7 6 Name 2K8KSRC Default 0 0 Bit 7: 2kHz/8kHz Source (2K8KSRC). This configuration bit specifies the source for the 2kHz and 8kHz outputs ...
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DS3102 Register Name: FSCR2 Register Description: Frame-Sync Configuration Register 2 Register Address: 7Bh Bit # 7 6 Name INDEP OCN Default 0 0 Bit 7: Independent Frame Sync and Multiframe Sync (INDEP). When this bit is set to 0, ...
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DS3102 Register Name: FSCR3 Register Description: Frame-Sync Configuration Register 3 Register Address: 7Ch Bit # 7 6 Name RECAL Default 0 0 Bit 7: Phase Offset Recalibration (RECAL). When set to 1, this configuration bit causes a recalibration of ...
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DS3102 Register Name: INTCR Register Description: Interrupt Configuration Register Register Address: 7Dh Bit # 7 6 Name — — Default 0 0 Bit 3: INTREQ Pin Mode (LOS). When GPO = 0, this bit selects the function of the ...
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DS3102 9. JTAG Test Access Port and Boundary Scan 9.1 JTAG Description The DS3102 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. the following items, which meet the requirements ...
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DS3102 9.2 JTAG TAP Controller State Machine Description This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge ...
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DS3102 Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. ...
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DS3102 9.3 JTAG Instruction Register and Instructions The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register ...
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DS3102 9.4 JTAG Test Registers IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An optional test register, the identification register, has been included in the device design used with ...
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DS3102 10. Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin with Respect to V Supply Voltage Range (V ) with Respect Supply Voltage Range (V ) with Respect to V DDIO Ambient Operating Temperature ...
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DS3102 Table 10-3. CMOS/TTL Pins = 1.8V 10 3.3V 5 DDIO PARAMETER Input High Voltage Input Low Voltage Input Leakage Input Leakage, Pins with Internal Pullup Resistor (50k typ) Input Leakage, Pins with Internal ...
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DS3102 Table 10-6. LVPECL Level-Compatible Output Pins = 1.8V 10 3.3V 5 DDIO PARAMETER Differential Output Voltage Output Offset (Common Mode) Voltage Difference in Magnitude of Output Differential Voltage for Complementary States Note 1: ...
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DS3102 Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins DS3102 LVPECL LEVEL- COMPATIBLE OUTPUTS 19-4617; Rev 5; 8/10 3.3V 82 82 50 OCnPOS 0.01F 50 OCnNEG 130 130 GND LVPECL RECEIVER 132 of 142 ...
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DS3102 10.2 Input Clock Timing Table 10-7. Input Clock Timing = 1.8V 10 3.3V 5 DDIO PARAMETER CMOS/TTL Input Pins Input Clock Period LVDS/LVPECL Input Pins Input Clock High, Low Time 10.3 Output Clock ...
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DS3102 10.4 SPI Interface Timing Table 10-10. SPI Interface Timing = 1.8V 10 3.3V 5 DDIO PARAMETER (Note 1) SCLK Frequency SCLK Cycle Time CS Setup to First SCLK Edge CS Hold Time After ...
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DS3102 Figure 10-4. SPI Interface Timing Diagram CPHA = SUC CYC SCLK, CPOL=0 t CLKH t SCLK, CLKL CPOL SUI HDI SDI SDO CPHA = SUC CYC SCLK, CPOL=0 ...
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DS3102 10.5 JTAG Interface Timing Table 10-11. JTAG Interface Timing = 1.8V 10 3.3V 5 DDIO PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 1) JTCLK to JTDI, JTMS Setup Time JTCLK to ...
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DS3102 10.6 Reset Pin Timing Table 10-12. Reset Pin Timing = 1.8V 10 3.3V 5 DDIO PARAMETER RST Low Time (Note 1) SONSDH, SRCSW Setup Time to RST SONSDH, SRCSW Hold Time from RST ...
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DS3102 11. Pin Assignments Table 11-1 lists pin assignments sorted in alphabetical order by pin name. arranged by pin number. Table 11-1. Pin Assignments Sorted by Signal Name PIN NAME PIN NUMBER AVDD_PLL1 AVDD_PLL2 C2 AVDD_PLL3 AVDD_PLL4 AVSS_PLL1 AVSS_PLL2 ...
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DS3102 Figure 11-1. Pin Assignment Diagram AVSS_PLL1 TEST INTREQ/ B AVDD_PLL1 LOS C REFCLK AVDD_PLL2 AVSS_PLL2 D OC4NEG OC4POS E OC5NEG OC5POS F AVSS_PLL3 AVDD_PLL3 AVDD_PLL4 G SRCSW AVSS_PLL4 H FSYNC OC6POS J MFSYNC OC6NEG High-Speed ...
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DS3102 12. Package Information For the latest package outline information and land patterns www.maxim-ic.com/packages. “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains ...
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DS3102 13. Acronyms and Abbreviations AIS Alarm Indication Signal AMI Alternate Mark Inversion APLL Analog Phase-Locked Loop BITS Building Integrated Timing Supply BPV Bipolar Violation DFS Digital Frequency Synthesis DPLL Digital Phase-Locked Loop ESF Extended Superframe EXZ Excessive Zeros ...
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... SRFAIL pin description to indicate state is high 7.5.1 and Section 7.7.6 deleted sentences that said the hard 7.6.7 to describe how to achieve GR-1244-compliant Maxim is a registered trademark of Maxim Integrated Products. to describe the phase monitor PAGES CHANGED — 46, 47, 48, 76, 119, 121 128 ...