DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 89

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DS3102GN

Manufacturer Part Number
DS3102GN
Description
Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
Manufacturer
Maxim Integrated Products
Datasheet

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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 5 to 0: Interrupt Enable for Input Clock Status Change (IC8 and IC[6:1]). Each of these bits is an
interrupt enable control for the corresponding bit in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Interrupt Enable for T0 DPLL State Change (STATE). This bit is an interrupt enable for the STATE bit in
the
Bit 6: Interrupt Enable for Selected Reference Failed (SRFAIL). This bit is an interrupt enable for the SRFAIL bit
in the
Bit 0: Interrupt Enable for Input Clock Status Change (IC9). This bit is an interrupt enable control for the IC9 bit
in the
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
MSR2
MSR2
MSR2
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
register.
register.
register.
STATE
IC8
7
0
7
0
SRFAIL
6
0
6
0
IER1
Interrupt Enable Register 1
43h
IER2
Interrupt Enable Register 2
44h
IC6
5
0
5
0
MSR1
IC5
4
0
4
0
register.
IC4
3
0
3
0
IC3
2
0
2
0
IC2
1
0
1
0
89 of 142
IC1
IC9
0
0
0
0

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