MAX3873AEGP Maxim Integrated Products, MAX3873AEGP Datasheet - Page 7

• Manufacturer Part Number: MAX3873AEGP
• Description: Timers & Support Products Low-Power, Compact 2 .5-2.7Gbps Clock Rec
• Manufacturer: Maxim Integrated Products
• Type: Clock Recoveryr

Specifications of MAX3873AEGP

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 112 mA
• Package / Case: QFN-20 EP
• Dc: 0509
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX3873A consists of a fully integrated phase-
locked loop (PLL), input amplifier, and CML output
buffers (Figure 5). The PLL consists of a phase/fre-
quency detector, a loop filter, and a voltage-controlled
oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Figure 5. Functional Diagram
SDI+
SDI-
17, 20
PIN
EP
10
11
12
13
14
15
16
18
19
AMP
V
CC
MAX3873A
Exposed Pad
VCC_BUF
Low-Power, Compact 2.5Gbps or 2.7Gbps
SCLKO+
SCLKEN
FREQUENCY
SCLKO-
PHASE AND
DETECTOR
NAME
SDO+
SDO-
GND
FIL+
LOL
FIL-
GND
_______________________________________________________________________________________
Detailed Description
Clock-Recovery and Data-Retiming IC
FASTRACK
FIL+
FILTER
LOOP
FIL-
C l ock Outp ut E nab l e, TTL Inp ut. W hen S C LKE N = op en or S C LKE N = hi g h, the cl ock outp uts
( S C LKO± ) ar e enab l ed . When S C LKE N = l ow , the cl ock outp uts ar e d i sab l ed and S C LKO ± = V
Negative Clock Output, CML. This output can be disabled by setting SCLKEN to low.
Positive Clock Output, CML. This output can be disabled by setting SCLKEN to low.
3.3V CML Output Buffer Supply Voltage
Negative Data Output, CML
Positive Data Output, CML
Loss-of-Lock Output, TTL (Active Low). The LOL output indicates a PLL lock failure.
Supply Ground
Negative PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.
Positive PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.
Ground. The exposed pad must be soldered to the circuit board ground for proper electrical and
thermal operation.
RATESET
VCO
Q
I
AMP
AMP
SDO+
SDO-
MODE
SCLKO+
SCLKO-
SCLKEN
LOL
The input amplifier provides internal 50Ω line termina-
tions and can accept a differential input amplitude from
50mV
amplifier is shown in Figure 9.
The phase detector incorporated in the MAX3873A pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
The digital frequency detector (FD) aids frequency
acquisition during startup conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the VCO outputs on each
edge of the data input signal. The FD drives the VCO
until the frequency difference is reduced to zero. Once
frequency acquisition is complete, the FD returns to a
neutral state.
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, C
is required to set the PLL damping ratio. See the
Design Procedure section for guidelines on selecting
this capacitor.
P-P
FUNCTION
to 1600mV
Pin Description (continued)
P-P
. The structure of the input
Loop Filter and VCO
Frequency Detector
Phase Detector
Input Amplifier
CC
.
F
7
,