MAX3873AEGP Maxim Integrated Products, MAX3873AEGP Datasheet - Page 9

• Manufacturer Part Number: MAX3873AEGP
• Description: Timers & Support Products Low-Power, Compact 2 .5-2.7Gbps Clock Rec
• Manufacturer: Maxim Integrated Products
• Type: Clock Recoveryr

Specifications of MAX3873AEGP

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 112 mA
• Package / Case: QFN-20 EP
• Dc: 0509
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX3873A has excellent jitter tolerance. Adding DJ
to the input will close the eye opening and result in
reduced sinusoidal jitter tolerance. It typically can toler-
ate more than 0.3UI
with a 2
istic jitter (DJ). This gives a total high-frequency jitter tol-
erance of 0.7UI. Refer to the Jitter Tolerance vs.
Pulse-Width Distortion and Jitter Tolerance vs.
Deterministic Jitter graphs in the Typical Operating
Characteristics section.
The MAX3873A’s digital CML outputs (SDO+, SDO-,
SCLKO+, SCLKO-) have selectable output amplitude
controlled by the MODE input. If the SCLKO outputs
are not used, they can be disabled (see the Supply
Current vs. Temperature graph in the Typical Operating
Characteristics section).
The structure of the high-speed digital outputs is shown
in Figure 8. The MODE input sets the current in the cur-
rent source, thereby controlling the output swing. The
SCLKEN input sets the current in the SCLKO current
source to 0mA, disabling the output.
The structure of the CML inputs (SDI±) is shown in Figure
9. Unless the CML input is DC-coupled to a CML output,
use AC-coupling with the CML inputs to avoid upsetting
the common-mode voltage.
Figure 8. CML Output Model
23
Input Deterministic Jitter Trade-Offs
MAX3873A
- 1 PRBS data stream with 0.4UI of determin-
Sinusoidal Jitter Tolerance and
Input and Output Terminations
Low-Power, Compact 2.5Gbps or 2.7Gbps
50Ω
V
_______________________________________________________________________________________
CC
P-P
of 10MHz jitter when measured
Clock-Recovery and Data-Retiming IC
50Ω
SCLKO ONLY
OUT+
OUT-
MODE
SCLKEN
The MAX3873A has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER of less than 10
is tested using a 2
of zeros to simulate the worst case. A CID tolerance of
2000 bits is typical.
The exposed-pad (EP), 20-pin QFN incorporates fea-
tures that provide a very low thermal-resistance path for
heat removal from the IC. The pad is electrical ground
on the MAX3873A and must be soldered to the circuit
board for proper thermal and electrical performance.
Circuit board layout and design can significantly affect
the MAX3873A’s performance. Use good high-frequency
design techniques, including minimizing ground induc-
tance and using controlled-impedance transmission
lines on the data and clock signals. Place power-supply
decoupling as close to the V
the input from the output signals to reduce feedthrough.
Figure 9. CML Input Model
SDI+
SDI-
Consecutive Identical Digits (CID)
V
V
MAX3873A
Applications Information
CC
CC
13
- 1 PRBS, substituting a long run
50Ω
Exposed-Pad Package
50Ω
CC
pins as possible. Isolate
-10
V
CC
. The CID tolerance
Layout
9