MAX3873AEGP Maxim Integrated Products, MAX3873AEGP Datasheet - Page 8

• Manufacturer Part Number: MAX3873AEGP
• Description: Timers & Support Products Low-Power, Compact 2 .5-2.7Gbps Clock Rec
• Manufacturer: Maxim Integrated Products
• Type: Clock Recoveryr

Specifications of MAX3873AEGP

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 112 mA
• Package / Case: QFN-20 EP
• Dc: 0509
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The loop filter output controls the on-chip LC VCO run-
ning at either 2.488GHz or 2.67GHz. The VCO provides
low phase noise and is trimmed to the correct
frequency. Clock jitter generation is typically 2ps
within a jitter band of 12kHz to 20MHz.
A loss-of-lock (LOL) monitor is incorporated in the
MAX3873A to indicate either a loss of frequency lock or
the absence of incoming data. Under loss-of-lock con-
ditions, LOL may momentarily assert high due to noise.
The MAX3873A is designed for both regenerator and
receiver applications. Its fully integrated PLL is a classic
second-order feedback system, with a loop bandwidth
(J
adjusted to set the loop damping. Figures 6 and 7 show
the open-loop and closed-loop transfer functions. The
PLL zero frequency, f
C
with C
For an overdamped system, the jitter peaking (J
second-order system can be approximated by:
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Figure 6. Open-Loop Transfer Function
8
F
BW
and can be approximated according to:
_______________________________________________________________________________________
) below 2.0MHz. The external capacitor, C
F
expressed in F.
H
O
(j2πf) (dB)
C
F
J
f
= 0.022μF
Z
P
= 2.4kHz
f
z
1
=
=
Z
20
, is a function of external capacitor
2
log
π
10
(
Setting the Loop Filter
3000
Design Procedure
⎛
⎜
⎝
Loss-of-Lock Monitor
1
C
f
Z
1
F
= 26kHz
+
= 2000pF
Ω
100
)
J
C
BW
f
z
F
1000
⎞
⎟
⎠
f (kHz)
F
, can be
P
) of a
RMS
For example, using C
of 0.2dB. Reducing C
instability. The recommended value is C
guarantee a maximum jitter peaking of less than 0.1dB.
C
or better.
The MAX3873A has a PLL fast-track (FASTRACK) mode
to decrease locking time in switched data applications.
In applications where the input data is switched from one
source to another, there is a brief period in which there is
no valid data input to the MAX3873A. In the absence of
input data, the PLL phase slowly drifts from the ideal
position. By enabling FASTRACK during reacquisition,
the time required to regain phase alignment is reduced.
This is accomplished by increasing the loop bandwidth
by approximately 50%.
The bandwidth of the MAX3873A is also linearly depen-
dent upon the transition density of the input data. By using
a preamble of 1200 bits of a 1–0 pattern during switching,
the loop bandwidth is increased by a factor of approxi-
mately 2 (Figure 3). Thus, by using a 1–0 pattern pream-
ble and enabling FASTRACK, the PLL bandwidth is
increased by a factor of approximately 3, resulting in the
fastest possible reacquisition of phase lock.
FASTRACK increases the rate at which the MAX3873A
acquires the proper phase, assuming that the VCO is
already running at the proper frequency. On startup con-
ditions, however, the VCO frequency is significantly differ-
ent from the input data, and the time required to lock to
the incoming data is increased to approximately 1.0ms.
Figure 7. Closed-Loop Transfer Function
F
must be a low TC, high-quality capacitor of type X7R
H(j2πf) (dB)
-3
0
1
F
F
10
= 2000pF results in jitter peaking
below 500pF might result in PLL
C
F
= 0.022μF
100
C
F
= 2000pF
1000
FASTRACK Mode
F
= 0.022µF to
f (kHz)