ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 26

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
end, the ispClock5600’s internal termination resistors are not available in these modes. Also note that output slew-
rate control is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate.
Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the
polarity of each of the two output signals from each bank may be controlled independently. In the case of differen-
tial output standards, the polarity of the differential pair may be selected.
Suggested Usage
Figure 20 shows a typical configuration for the ispClock5600’s output driver when configured to drive an LVTTL or
LVCMOS load. The ispClock5600’s output impedance should be set to match the characteristic impedance of the
transmission line being driven. The far end of the transmission line should be left open, with no termination resis-
tors.
Figure 20. Configuration for LVTTL/LVCMOS Output Modes
Figure 21 shows a typical configuration for the ispClock5600’s output driver when configured to drive SSTL2,
SSTL3, or HSTL loads. The ispClock5600’s output impedance should be set to 40Ω for driving SSTL2 or SSTL3
loads and to the ≈20Ω setting for driving HSTL. The far end of the transmission line must be terminated to an
appropriate VTT voltage through a 50Ω resistor.
Figure 21. Configuration for SSTL2, SSTL3, and HSTL Output Modes
While supporting single-ended HSTL and SSTL outputs, the ispClock5600 does not support differential HSTL or
SSTL outputs. Although complementary HSTL and SSTL signals may be generated by using both an inverted out-
put and a non-inverted output similarly configured, the resulting signal pair may not meet the JEDEC differential
HSTL specifications for common mode voltage or crossover voltage.
Figure 22 shows a typical configuration for the ispClock5600’s output driver when configured to drive LVDS or dif-
ferential LVPECL loads. The ispClock5600’s output impedance is disengaged when the driver is set to LVDS or
SSTL/HSTL
LVCMOS/LVTTL
Mode
Ro : 40 (SSTL)
Mode
ispClock5600
≈20Ω (HSTL)
ispClock5600
Ro = Zo
26
Zo=50Ω
Zo
ispClock5600 Family Data Sheet
VREF
RT=50
VTT
LVCMOS/LVTTL
Receiver
SSTL/HSTL
Receiver