ispPAC-CLK5304S-01T48I Lattice, ispPAC-CLK5304S-01T48I Datasheet - Page 26

Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I

ispPAC-CLK5304S-01T48I

Manufacturer Part Number
ispPAC-CLK5304S-01T48I
Description
Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
Manufacturer
Lattice
Datasheet

Specifications of ispPAC-CLK5304S-01T48I

Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Maximum Operating Temperature
85 C
Package / Case
TQFP-48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-CLK5304S-01T48I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 21. Configuration for SSTL2, SSTL3, and HSTL Output Modes
ispClock5300S Configurations
The ispClock5300S device can be configured to operate in four modes. They are:
The output routing matrix of the ispClock5300S provides up to three independent any-to-any paths from inputs to
outputs:
Zero Delay Buffer Mode
Figure 22 shows the ispClock5300S device configured to operate in the Zero Delay Buffer mode. The Clock input
can be single ended or differential. Two single ended clocks can be selected by the use of REFSEL pin and if the
input is configured as a differential the REFSEL pin should be connected to GNDD. The input clock then drives the
Phase frequency detector of the PLL. Up to 3 output clock frequencies can be generated from the input reference
clock by the use of V-dividers at the output of PLL. Any V-divider output can be connected to any of the output pins.
However, one of the V-dividers should be used in the feedback path to set the PLL operating frequency. The PLL
can operate with internal or external feedback path.
In this mode, the skew control mechanism is active for all outputs.
Zero Delay Buffer Mode
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Non-Zero Delay Buffer mode 1
Non-Zero Delay Buffer Mode 2
From any V-Dividers to any output in ZDB mode or PLL Bypass modes
From selected clock via REFSEL pin to any output (note single ended reference clock)
From the other clock not selected by REFSEL pin to any output
Ro : 40 (SSTL)
SSTL/HSTL/eHSTL
Mode
20 (HSTL, eHSTL)
ispClock5300S
26
Zo=50
ispClock5300S Family Data Sheet
VREF
RT=50
VTT
SSTL/HSTL/eHSTL
Receiver

Related parts for ispPAC-CLK5304S-01T48I